Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Renesas Solutions Migo-R board |
| 4 | * |
| 5 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __MIGO_R_H |
| 9 | #define __MIGO_R_H |
| 10 | |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 11 | #define CONFIG_CPU_SH7722 1 |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 12 | |
Vladimir Zapolskiy | 18a40e8 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 13 | #define CONFIG_DISPLAY_BOARDINFO |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 14 | |
| 15 | /* SMC9111 */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 16 | #define CONFIG_SMC91111 |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 17 | #define CONFIG_SMC91111_BASE (0xB0000000) |
| 18 | |
| 19 | /* MEMORY */ |
| 20 | #define MIGO_R_SDRAM_BASE (0x8C000000) |
| 21 | #define MIGO_R_FLASH_BASE_1 (0xA0000000) |
| 22 | #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) |
| 23 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 25 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 26 | |
| 27 | /* SCIF */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 28 | #define CONFIG_CONS_SCIF0 1 |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 29 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 30 | #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) |
| 31 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 32 | |
| 33 | /* Enable alternate, more extensive, memory test */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 34 | /* Scratch address used by the alternate memory test */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 36 | |
| 37 | /* Enable temporary baudrate change while serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 39 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 41 | /* maybe more, but if so u-boot doesn't know about it... */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 43 | /* default load address for scripts ?!? */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 45 | |
| 46 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 48 | /* Monitor size */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 50 | /* Size of DRAM reserved for malloc() use */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 53 | |
| 54 | /* FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 56 | /* print 'E' for empty sector on flinfo */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 58 | /* Physical start address of Flash memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 60 | /* Max number of sectors on each Flash chip */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 62 | |
| 63 | /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 65 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 66 | |
| 67 | /* Timeout for Flash erase operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 69 | /* Timeout for Flash write operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 71 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 73 | /* Timeout for Flash clear lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 75 | |
| 76 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 77 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 78 | |
| 79 | /* ENV setting */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 80 | #define CONFIG_ENV_OVERWRITE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 82 | |
| 83 | /* Board Clock */ |
| 84 | #define CONFIG_SYS_CLK_FREQ 33333333 |
Nobuhiro Iwamatsu | 684a501 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 85 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
goda.yusuke | c2042f5 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 86 | |
| 87 | #endif /* __MIGO_R_H */ |