| Marek Vasut | 3ebb919 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * include/configs/condor.h |
| 4 | * This file is Condor board configuration. |
| 5 | * |
| 6 | * Copyright (C) 2019 Renesas Electronics Corporation |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONDOR_H |
| 10 | #define __CONDOR_H |
| 11 | |
| 12 | #include "rcar-gen3-common.h" |
| 13 | |
| 14 | /* Ethernet RAVB */ |
| 15 | #define CONFIG_BITBANGMII |
| 16 | #define CONFIG_BITBANGMII_MULTI |
| 17 | |
| 18 | /* Environment compatibility */ |
| Marek Vasut | 3ebb919 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 19 | |
| 20 | /* SH Ether */ |
| 21 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 22 | #define CONFIG_SH_ETHER_PHY_ADDR 0x1 |
| 23 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII |
| 24 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK |
| 25 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE |
| 26 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
| 27 | #define CONFIG_BITBANGMII |
| 28 | #define CONFIG_BITBANGMII_MULTI |
| 29 | |
| 30 | /* Board Clock */ |
| 31 | /* XTAL_CLK : 33.33MHz */ |
| 32 | #define CONFIG_SYS_CLK_FREQ 33333333u |
| 33 | |
| 34 | /* Generic Timer Definitions (use in assembler source) */ |
| 35 | #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
| 36 | |
| 37 | #endif /* __CONDOR_H */ |