| Konstantin Porotchkin | a0ba97e | 2021-01-17 17:19:49 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 1335483 | 2016-05-25 08:23:31 +0200 | [diff] [blame] | 2 | /* |
| Konstantin Porotchkin | a0ba97e | 2021-01-17 17:19:49 +0200 | [diff] [blame^] | 3 | * Copyright (C) 2016- 2021 Marvell International Ltd. |
| Stefan Roese | 1335483 | 2016-05-25 08:23:31 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and |
| 8 | * one CP110. |
| 9 | */ |
| 10 | |
| Konstantin Porotchkin | 9eb3468 | 2017-02-08 17:34:11 +0200 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
| Konstantin Porotchkin | a0ba97e | 2021-01-17 17:19:49 +0200 | [diff] [blame^] | 12 | #include "armada-common.dtsi" |
| 13 | #include "armada-8k.dtsi" |
| Stefan Roese | 1335483 | 2016-05-25 08:23:31 +0200 | [diff] [blame] | 14 | #include "armada-ap806-quad.dtsi" |
| Konstantin Porotchkin | a0ba97e | 2021-01-17 17:19:49 +0200 | [diff] [blame^] | 15 | |
| 16 | /* CP110-0 Settings */ |
| 17 | #define CP110_NAME cp0 |
| 18 | #define CP110_NUM 0 |
| 19 | |
| 20 | #include "armada-cp110.dtsi" |
| 21 | |
| 22 | #undef CP110_NAME |
| 23 | #undef CP110_NUM |
| Stefan Roese | 1335483 | 2016-05-25 08:23:31 +0200 | [diff] [blame] | 24 | |
| 25 | / { |
| 26 | model = "Marvell Armada 7040"; |
| 27 | compatible = "marvell,armada7040", "marvell,armada-ap806-quad", |
| 28 | "marvell,armada-ap806"; |
| 29 | }; |
| Konstantin Porotchkin | a0ba97e | 2021-01-17 17:19:49 +0200 | [diff] [blame^] | 30 | |
| 31 | &cp0_pinctl { |
| 32 | compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl"; |
| 33 | bank-name ="cp0-110"; |
| 34 | |
| 35 | cp0_i2c0_pins: cp0-i2c-pins-0 { |
| 36 | marvell,pins = < 37 38 >; |
| 37 | marvell,function = <2>; |
| 38 | }; |
| 39 | cp0_i2c1_pins: cp0-i2c-pins-1 { |
| 40 | marvell,pins = < 35 36 >; |
| 41 | marvell,function = <2>; |
| 42 | }; |
| 43 | cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { |
| 44 | marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; |
| 45 | marvell,function = <3>; |
| 46 | }; |
| 47 | cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { |
| 48 | marvell,pins = < 44 45 46 47 48 49 50 51 |
| 49 | 52 53 54 55 >; |
| 50 | marvell,function = <1>; |
| 51 | }; |
| 52 | cp0_pca0_pins: cp0-pca0_pins { |
| 53 | marvell,pins = <62>; |
| 54 | marvell,function = <0>; |
| 55 | }; |
| 56 | cp0_sdhci_pins: cp0-sdhi-pins-0 { |
| 57 | marvell,pins = < 56 57 58 59 60 61 >; |
| 58 | marvell,function = <14>; |
| 59 | }; |
| 60 | cp0_spi0_pins: cp0-spi-pins-0 { |
| 61 | marvell,pins = < 13 14 15 16 >; |
| 62 | marvell,function = <3>; |
| 63 | }; |
| 64 | }; |