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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a0ba97e5617fc636992fb0bab7cabc17a17b3bdd / . / arch / arm / dts / armada-cp110.dtsi
blob: 8241c643b04e890d7eb07c29ddef3972531c5c15 [file] [log] [blame]
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016- 2021 Marvell International Ltd.
4 */
5
6/*
7 * Generic Device Tree describing Marvell Armada CP-110 device
8 */
9
10#include <dt-bindings/comphy/comphy_data.h>
11
12#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
13#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
14
15#define CP110_PCIEx_REG0_BASE(iface) \
16 (CP110_BASE + 0x600000 + (iface) * 0x20000)
17#define CP110_PCIEx_REG1_BASE(iface) \
18 (CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface))
19#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \
20 (iface) * 0x4000)
21
22/ {
23 CP110_NAME {
24 #address-cells = <2>;
25 #size-cells = <2>;
26 compatible = "simple-bus";
27 interrupt-parent = <&gic>;
28 ranges;
29
30 config-space {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 interrupt-parent = <&gic>;
35 ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
36
37 CP110_LABEL(mdio): mdio@12a200 {
38 #address-cells = <1>;
39 #size-cells = <0>;
40 compatible = "marvell,orion-mdio";
41 reg = <0x12a200 0x10>;
42 device-name = CP110_STRING_LABEL(mdio);
43 status = "disabled";
44 };
45
46 CP110_LABEL(xmdio): mdio@12a600 {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 compatible = "marvell,xmdio";
50 reg = <0x12a600 0x200>;
51 device-name = CP110_STRING_LABEL(xmdio);
52 status = "disabled";
53 };
54
55 CP110_LABEL(sar-reg) {
56 compatible = "marvell,sample-at-reset-common",
57 "marvell,sample-at-reset-cp110";
58 reg = <0x400200 0x8>;
59 sar-driver = "cp110_sar";
60 sar-name = CP110_STRING_LABEL(sar);
61 status = "okay";
62 };
63
64 CP110_LABEL(syscon0): system-controller@440000 {
65 compatible = "marvell,cp110-system-controller0",
66 "syscon";
67 reg = <0x440000 0x1000>;
68 #clock-cells = <2>;
69 core-clock-output-names =
70 "cpm-apll", "cpm-ppv2-core", "cpm-eip",
71 "cpm-core", "cpm-nand-core";
72 gate-clock-output-names =
73 "cpm-audio", "cpm-communit", "cpm-nand",
74 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
75 "cpm-mg-core", "cpm-xor1", "cpm-xor0",
76 "cpm-gop-dp", "none", "cpm-pcie_x10",
77 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
78 "cpm-sata", "cpm-sata-usb", "cpm-main",
79 "cpm-sd-mmc", "none", "none",
80 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
81 "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
82 };
83
84 CP110_LABEL(pinctl): pinctl@440000 {
85 compatible = "marvell,mvebu-pinctrl";
86 reg = <0x440000 0x20>;
87 pin-count = <63>;
88 max-func = <0xf>;
89 };
90
91 CP110_LABEL(gpio0): gpio@440100 {
92 compatible = "marvell,orion-gpio";
93 reg = <0x440100 0x40>;
94 ngpios = <32>;
95 gpiobase = <20>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 };
99
100 CP110_LABEL(gpio1): gpio@440140 {
101 compatible = "marvell,orion-gpio";
102 reg = <0x440140 0x40>;
103 ngpios = <31>;
104 gpiobase = <52>;
105 gpio-controller;
106 #gpio-cells = <2>;
107 };
108
109 CP110_LABEL(sata0): sata@540000 {
110 compatible = "marvell,armada-8k-ahci";
111 reg = <0x540000 0x30000>;
112 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&CP110_LABEL(syscon0) 1 15>;
114 status = "disabled";
115 };
116
117 CP110_LABEL(usb3_0): usb3@500000 {
118 compatible = "marvell,armada-8k-xhci",
119 "generic-xhci";
120 reg = <0x500000 0x4000>;
121 dma-coherent;
122 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&CP110_LABEL(syscon0) 1 22>;
124 status = "disabled";
125 };
126
127 CP110_LABEL(usb3_1): usb3@510000 {
128 compatible = "marvell,armada-8k-xhci",
129 "generic-xhci";
130 reg = <0x510000 0x4000>;
131 dma-coherent;
132 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&CP110_LABEL(syscon0) 1 23>;
134 status = "disabled";
135 };
136
137 CP110_LABEL(spi0): spi@700600 {
138 compatible = "marvell,armada-380-spi";
139 reg = <0x700600 0x50>;
140 #address-cells = <0x1>;
141 #size-cells = <0x0>;
142 cell-index = <1>;
143 spi-max-frequency = <50000000>;
144 clocks = <&CP110_LABEL(syscon0) 0 3>;
145 status = "disabled";
146 };
147
148 CP110_LABEL(spi1): spi@700680 {
149 compatible = "marvell,armada-380-spi";
150 reg = <0x700680 0x50>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 cell-index = <2>;
154 spi-max-frequency = <50000000>;
155 clocks = <&CP110_LABEL(syscon0) 1 21>;
156 status = "disabled";
157 };
158
159 CP110_LABEL(i2c0): i2c@701000 {
160 compatible = "marvell,mv78230-i2c";
161 reg = <0x701000 0x20>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&CP110_LABEL(syscon0) 1 21>;
166 status = "disabled";
167 };
168
169 CP110_LABEL(i2c1): i2c@701100 {
170 compatible = "marvell,mv78230-i2c";
171 reg = <0x701100 0x20>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&CP110_LABEL(syscon0) 1 21>;
176 status = "disabled";
177 };
178
179 CP110_LABEL(mss_i2c0): i2c@211000 {
180 compatible = "marvell,mv78230-i2c";
181 reg = <0x211000 0x20>;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 status = "disabled";
185 };
186
187 CP110_LABEL(comphy): comphy@441000 {
188 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
189 reg = <0x441000 0x8>,
190 <0x120000 0x8>;
191 mux-bitcount = <4>;
192 max-lanes = <6>;
193 };
194
195 CP110_LABEL(utmi0): utmi@580000 {
196 compatible = "marvell,mvebu-utmi-2.6.0";
197 reg = <0x580000 0x1000>, /* utmi-unit */
198 <0x440420 0x4>, /* usb-cfg */
199 <0x440440 0x4>; /* utmi-cfg */
200 utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
201 status = "disabled";
202 };
203
204 CP110_LABEL(utmi1): utmi@581000 {
205 compatible = "marvell,mvebu-utmi-2.6.0";
206 reg = <0x581000 0x1000>, /* utmi-unit */
207 <0x440420 0x4>, /* usb-cfg */
208 <0x440444 0x4>; /* utmi-cfg */
209 utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
210 status = "disabled";
211 };
212
213 CP110_LABEL(sdhci0): sdhci@780000 {
214 compatible = "marvell,armada-8k-sdhci";
215 reg = <0x780000 0x300>;
216 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
217 dma-coherent;
218 status = "disabled";
219 };
220
221 CP110_LABEL(nand): nand@720000 {
222 compatible = "marvell,armada-8k-nand-controller",
223 "marvell,armada370-nand-controller";
224 reg = <0x720000 0x54>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 clocks = <&CP110_LABEL(syscon0) 1 2>;
228 nand-enable-arbiter;
229 num-cs = <1>;
230 nand-ecc-strength = <8>;
231 nand-ecc-step-size = <512>;
232 marvell,system-controller = <&CP110_LABEL(syscon0)>;
233 status = "disabled";
234 };
235
236 CP110_LABEL(ethernet): ethernet@0 {
237 compatible = "marvell,armada-7k-pp22";
238 reg = <0x0 0x100000>, <0x129000 0xb000>;
239 clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>;
240 clock-names = "pp_clk", "gop_clk", "mg_clk";
241 status = "disabled";
242 dma-coherent;
243
244 CP110_LABEL(eth0): eth0 {
245 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
246 port-id = <0>;
247 gop-port-id = <0>;
248 status = "disabled";
249 };
250
251 CP110_LABEL(eth1): eth1 {
252 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
253 port-id = <1>;
254 gop-port-id = <2>;
255 status = "disabled";
256 };
257
258 CP110_LABEL(eth2): eth2 {
259 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
260 port-id = <2>;
261 gop-port-id = <3>;
262 status = "disabled";
263 };
264 };
265 };
266
267 CP110_LABEL(pcie0): pcie0@600000 {
268 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
269 reg =
270 <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>,
271 /* Last 512KB of mem space */
272 <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>;
273 reg-names = "ctrl", "config";
274 #address-cells = <3>;
275 #size-cells = <2>;
276 #interrupt-cells = <1>;
277 device_type = "pci";
278 dma-coherent;
279
280 bus-range = <0 0xff>;
281 ranges =
282 /* non-prefetchable memory */
283 <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0))
284 U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0))
285 U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0))
286 U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>;
287 interrupt-map-mask = <0 0 0 0>;
288 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
289 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
290 num-lanes = <1>;
291 clocks = <&CP110_LABEL(syscon0) 1 13>;
292 status = "disabled";
293 };
294
295 CP110_LABEL(pcie1): pcie1@620000 {
296 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
297 reg =
298 <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>,
299 /* Last 512KB of mem space */
300 <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>;
301 reg-names = "ctrl", "config";
302 #address-cells = <3>;
303 #size-cells = <2>;
304 #interrupt-cells = <1>;
305 device_type = "pci";
306 dma-coherent;
307
308 bus-range = <0 0xff>;
309 ranges =
310 /* non-prefetchable memory */
311 <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1))
312 U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1))
313 U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1))
314 U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>;
315 interrupt-map-mask = <0 0 0 0>;
316 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
317 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
318
319 num-lanes = <1>;
320 clocks = <&CP110_LABEL(syscon0) 1 11>;
321 status = "disabled";
322 };
323
324 CP110_LABEL(pcie2): pcie2@640000 {
325 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
326 reg =
327 <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>,
328 /* Last 64KB of mem space */
329 <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>;
330 reg-names = "ctrl", "config";
331 #address-cells = <3>;
332 #size-cells = <2>;
333 #interrupt-cells = <1>;
334 device_type = "pci";
335 dma-coherent;
336
337 bus-range = <0 0xff>;
338 ranges =
339 /* non-prefetchable memory */
340 <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2))
341 U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2))
342 U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2))
343 U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>;
344 interrupt-map-mask = <0 0 0 0>;
345 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
346 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
347
348 num-lanes = <1>;
349 clocks = <&CP110_LABEL(syscon0) 1 12>;
350 status = "disabled";
351 };
352 };
353};