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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * armboot - Startup Code for ARM720 CPU-core
3 *
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
wdenkdc7c9a12003-03-26 06:55:25 +000027#include "config.h"
28#include "version.h"
29
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start: b reset
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
45 ldr pc, _data_abort
46 ldr pc, _not_used
47 ldr pc, _irq
48 ldr pc, _fiq
49
50_undefined_instruction: .word undefined_instruction
51_software_interrupt: .word software_interrupt
52_prefetch_abort: .word prefetch_abort
53_data_abort: .word data_abort
54_not_used: .word not_used
55_irq: .word irq
56_fiq: .word fiq
57
58 .balignl 16,0xdeadbeef
59
60
61/*
62 *************************************************************************
63 *
64 * Startup Code (reset vector)
65 *
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
73
wdenkdc7c9a12003-03-26 06:55:25 +000074_TEXT_BASE:
75 .word TEXT_BASE
76
77.globl _armboot_start
78_armboot_start:
79 .word _start
80
81/*
wdenkf6e20fc2004-02-08 19:38:38 +000082 * These are defined in the board-specific linker script.
wdenkdc7c9a12003-03-26 06:55:25 +000083 */
wdenkf6e20fc2004-02-08 19:38:38 +000084.globl _bss_start
85_bss_start:
86 .word __bss_start
87
88.globl _bss_end
89_bss_end:
90 .word _end
wdenkdc7c9a12003-03-26 06:55:25 +000091
wdenkdc7c9a12003-03-26 06:55:25 +000092#ifdef CONFIG_USE_IRQ
93/* IRQ stack memory (calculated at run-time) */
94.globl IRQ_STACK_START
95IRQ_STACK_START:
96 .word 0x0badc0de
97
98/* IRQ stack memory (calculated at run-time) */
99.globl FIQ_STACK_START
100FIQ_STACK_START:
101 .word 0x0badc0de
102#endif
103
104
105/*
106 * the actual reset code
107 */
108
109reset:
110 /*
wdenk8bde7f72003-06-27 21:31:46 +0000111 * set the cpu to SVC32 mode
112 */
113 mrs r0,cpsr
114 bic r0,r0,#0x1f
wdenk9d5028c2004-11-21 00:06:33 +0000115 orr r0,r0,#0xd3 /* was 13 */
wdenk8bde7f72003-06-27 21:31:46 +0000116 msr cpsr,r0
wdenkdc7c9a12003-03-26 06:55:25 +0000117
wdenk9d5028c2004-11-21 00:06:33 +0000118#ifdef CONFIG_BOOTBINFUNC
119/* code based on entry.S from ATMEL */
120#define AT91C_BASE_CKGR 0xFFFFFC20
121#define CKGR_MOR 0
122 /* Get the CKGR Base Address */
123 ldr r1, =AT91C_BASE_CKGR
124
125/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
126/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
127 ldr r0, =0x0000FF01
128 str r0, [r1, #CKGR_MOR]
129 /* Add loop to compensate Main Oscillator startup time */
130 ldr r0, =0x00000010
131LoopOsc:
132 subs r0, r0, #1
133 bhi LoopOsc
134
135 /* scratch stack */
136 ldr r1, =0x00204000
137 /* Insure word alignment */
138 bic r1, r1, #3
139 /* Init stack SYS */
140 mov sp, r1
141 /*
142 * This does a lot more than just set up the memory, which
143 * is why it's called lowlevelinit
144 */
145 bl lowlevelinit /* in memsetup.S */
146 bl icache_enable;
147 /*------------------------------------
148 Read/modify/write CP15 control register
149 -------------------------------------
150 read cp15 control register (cp15 r1) in r0
151 ------------------------------------*/
152 mrc p15, 0, r0, c1, c0, 0
153 /* Reset bit :Little Endian end fast bus mode */
154 ldr r3, =0xC0000080
155 /* Set bit :Asynchronous clock mode, Not Fast Bus */
156 ldr r4, =0xC0000000
157 bic r0, r0, r3
158 orr r0, r0, r4
159 /* write r0 in cp15 control register (cp15 r1) */
160 mcr p15, 0, r0, c1, c0, 0
161#endif /* CONFIG_BOOTBINFUNC */
wdenkdc7c9a12003-03-26 06:55:25 +0000162 /*
163 * relocate exeception table
164 */
165 ldr r0, =_start
166 ldr r1, =0x0
167 mov r2, #16
168copyex:
169 subs r2, r2, #1
170 ldr r3, [r0], #4
171 str r3, [r1], #4
172 bne copyex
173
174 /*
wdenk8bde7f72003-06-27 21:31:46 +0000175 * we do sys-critical inits only at reboot,
176 * not when booting from ram!
177 */
wdenkdc7c9a12003-03-26 06:55:25 +0000178#ifdef CONFIG_INIT_CRITICAL
wdenk8bde7f72003-06-27 21:31:46 +0000179 bl cpu_init_crit
wdenkdc7c9a12003-03-26 06:55:25 +0000180#endif
181
wdenk9d5028c2004-11-21 00:06:33 +0000182#ifdef CONFIG_BOOTBINFUNC
183relocate: /* relocate U-Boot to RAM */
184 adr r0, _start /* r0 <- current position of code */
185 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
186 cmp r0, r1 /* don't reloc during debug */
187 beq stack_setup
188
189 ldr r2, _armboot_start
190 ldr r3, _bss_start
191 sub r2, r3, r2 /* r2 <- size of armboot */
192 add r2, r0, r2 /* r2 <- source end address */
193
194copy_loop:
195 ldmia r0!, {r3-r10} /* copy from source address [r0] */
196 stmia r1!, {r3-r10} /* copy to target address [r1] */
197 cmp r0, r2 /* until source end addreee [r2] */
198 ble copy_loop
199#endif /* CONFIG_BOOTBINFUNC */
200
wdenka8c7c702003-12-06 19:49:23 +0000201 /* Set up the stack */
202stack_setup:
203 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
204 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
205 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
206#ifdef CONFIG_USE_IRQ
207 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
208#endif
209 sub sp, r0, #12 /* leave 3 words for abort-stack */
210
wdenkf6e20fc2004-02-08 19:38:38 +0000211clear_bss:
212 ldr r0, _bss_start /* find start of bss segment */
wdenkf6e20fc2004-02-08 19:38:38 +0000213 ldr r1, _bss_end /* stop here */
214 mov r2, #0x00000000 /* clear */
215
216clbss_l:str r2, [r0] /* clear loop... */
217 add r0, r0, #4
218 cmp r0, r1
wdenka1191902005-01-09 17:12:27 +0000219 ble clbss_l
wdenkf6e20fc2004-02-08 19:38:38 +0000220
wdenk8bde7f72003-06-27 21:31:46 +0000221 ldr pc,_start_armboot
wdenkdc7c9a12003-03-26 06:55:25 +0000222
223_start_armboot: .word start_armboot
224
225/*
226 *************************************************************************
227 *
228 * CPU_init_critical registers
229 *
230 *************************************************************************
231 */
232
233cpu_init_crit:
wdenk9d5028c2004-11-21 00:06:33 +0000234 /* do nothing for now */
wdenkdc7c9a12003-03-26 06:55:25 +0000235 mov pc, lr
236
237
wdenkdc7c9a12003-03-26 06:55:25 +0000238/*
239 *************************************************************************
240 *
241 * Interrupt handling
242 *
243 *************************************************************************
244 */
245
246@
247@ IRQ stack frame.
248@
249#define S_FRAME_SIZE 72
250
251#define S_OLD_R0 68
252#define S_PSR 64
253#define S_PC 60
254#define S_LR 56
255#define S_SP 52
256
257#define S_IP 48
258#define S_FP 44
259#define S_R10 40
260#define S_R9 36
261#define S_R8 32
262#define S_R7 28
263#define S_R6 24
264#define S_R5 20
265#define S_R4 16
266#define S_R3 12
267#define S_R2 8
268#define S_R1 4
269#define S_R0 0
270
271#define MODE_SVC 0x13
272#define I_BIT 0x80
273
274/*
275 * use bad_save_user_regs for abort/prefetch/undef/swi ...
276 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
277 */
278
279 .macro bad_save_user_regs
280 sub sp, sp, #S_FRAME_SIZE
281 stmia sp, {r0 - r12} @ Calling r0-r12
282 add r8, sp, #S_PC
283
wdenkf6e20fc2004-02-08 19:38:38 +0000284 ldr r2, _armboot_start
285 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
286 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
wdenkdc7c9a12003-03-26 06:55:25 +0000287 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
288 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
289
290 add r5, sp, #S_SP
291 mov r1, lr
292 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
293 mov r0, sp
294 .endm
295
296 .macro irq_save_user_regs
297 sub sp, sp, #S_FRAME_SIZE
298 stmia sp, {r0 - r12} @ Calling r0-r12
299 add r8, sp, #S_PC
300 stmdb r8, {sp, lr}^ @ Calling SP, LR
301 str lr, [r8, #0] @ Save calling PC
302 mrs r6, spsr
303 str r6, [r8, #4] @ Save CPSR
304 str r0, [r8, #8] @ Save OLD_R0
305 mov r0, sp
306 .endm
307
308 .macro irq_restore_user_regs
309 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
310 mov r0, r0
311 ldr lr, [sp, #S_PC] @ Get PC
312 add sp, sp, #S_FRAME_SIZE
313 subs pc, lr, #4 @ return & move spsr_svc into cpsr
314 .endm
315
316 .macro get_bad_stack
wdenkf6e20fc2004-02-08 19:38:38 +0000317 ldr r13, _armboot_start @ setup our mode stack
318 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
319 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
wdenkdc7c9a12003-03-26 06:55:25 +0000320
321 str lr, [r13] @ save caller lr / spsr
322 mrs lr, spsr
323 str lr, [r13, #4]
324
325 mov r13, #MODE_SVC @ prepare SVC-Mode
326 msr spsr_c, r13
327 mov lr, pc
328 movs pc, lr
329 .endm
330
331 .macro get_irq_stack @ setup IRQ stack
332 ldr sp, IRQ_STACK_START
333 .endm
334
335 .macro get_fiq_stack @ setup FIQ stack
336 ldr sp, FIQ_STACK_START
337 .endm
338
339/*
340 * exception handlers
341 */
342 .align 5
343undefined_instruction:
344 get_bad_stack
345 bad_save_user_regs
346 bl do_undefined_instruction
347
348 .align 5
349software_interrupt:
350 get_bad_stack
351 bad_save_user_regs
352 bl do_software_interrupt
353
354 .align 5
355prefetch_abort:
356 get_bad_stack
357 bad_save_user_regs
358 bl do_prefetch_abort
359
360 .align 5
361data_abort:
362 get_bad_stack
363 bad_save_user_regs
364 bl do_data_abort
365
366 .align 5
367not_used:
368 get_bad_stack
369 bad_save_user_regs
370 bl do_not_used
371
372#ifdef CONFIG_USE_IRQ
373
374 .align 5
375irq:
376 get_irq_stack
377 irq_save_user_regs
378 bl do_irq
379 irq_restore_user_regs
380
381 .align 5
382fiq:
383 get_fiq_stack
384 /* someone ought to write a more effiction fiq_save_user_regs */
385 irq_save_user_regs
386 bl do_fiq
387 irq_restore_user_regs
388
389#else
390
391 .align 5
392irq:
393 get_bad_stack
394 bad_save_user_regs
395 bl do_irq
396
397 .align 5
398fiq:
399 get_bad_stack
400 bad_save_user_regs
401 bl do_fiq
402
403#endif
404
405 .align 5
406.globl reset_cpu
407reset_cpu:
408 mov pc, r0