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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02002/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02006 */
7
8#include <config.h>
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +05309#include <common.h>
Simon Glass9b4a2052019-12-28 10:45:05 -070010#include <init.h>
Lei Wena7efd712011-10-18 20:11:42 +053011#include <asm/io.h>
12#include <asm/arch/cpu.h>
Stefan Roese3dc23f72014-10-22 12:13:06 +020013#include <asm/arch/soc.h>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020014
Stefan Roese81e33f42015-12-21 13:56:33 +010015#if defined(CONFIG_ARCH_MVEBU)
16/* Use common XOR definitions for A3x and AXP */
Stefan Roese0ceb2da2015-08-06 14:43:13 +020017#include "../../../drivers/ddr/marvell/axp/xor.h"
18#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
Stefan Roese8a83c652015-08-03 13:15:31 +020019#endif
20
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +053021DECLARE_GLOBAL_DATA_PTR;
22
Stefan Roese96c5f082014-10-22 12:13:13 +020023struct sdram_bank {
Holger Brunckcf37c5d2012-07-20 02:34:24 +000024 u32 win_bar;
25 u32 win_sz;
26};
27
Stefan Roese96c5f082014-10-22 12:13:13 +020028struct sdram_addr_dec {
29 struct sdram_bank sdram_bank[4];
Holger Brunckcf37c5d2012-07-20 02:34:24 +000030};
31
Stefan Roese96c5f082014-10-22 12:13:13 +020032#define REG_CPUCS_WIN_ENABLE (1 << 0)
33#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
34#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
35#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
Gerlando Falauto45515162012-07-20 02:34:25 +000036
Stefan Roesea8483502018-10-22 14:21:17 +020037#ifndef MVEBU_SDRAM_SIZE_MAX
38#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
39#endif
Stefan Roesea8b57a92015-08-10 15:11:27 +020040
Stefan Roese0ceb2da2015-08-06 14:43:13 +020041#define SCRUB_MAGIC 0xbeefdead
42
43#define SCRB_XOR_UNIT 0
44#define SCRB_XOR_CHAN 1
45#define SCRB_XOR_WIN 0
46
47#define XEBARX_BASE_OFFS 16
48
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020049/*
Stefan Roese96c5f082014-10-22 12:13:13 +020050 * mvebu_sdram_bar - reads SDRAM Base Address Register
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020051 */
Stefan Roese96c5f082014-10-22 12:13:13 +020052u32 mvebu_sdram_bar(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020053{
Stefan Roese96c5f082014-10-22 12:13:13 +020054 struct sdram_addr_dec *base =
55 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020056 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000057 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020058
59 if ((!enable) || (bank > BANK3))
60 return 0;
61
Holger Brunckcf37c5d2012-07-20 02:34:24 +000062 result = readl(&base->sdram_bank[bank].win_bar);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020063 return result;
64}
65
66/*
Stefan Roese96c5f082014-10-22 12:13:13 +020067 * mvebu_sdram_bs_set - writes SDRAM Bank size
Gerlando Falauto45515162012-07-20 02:34:25 +000068 */
Stefan Roese96c5f082014-10-22 12:13:13 +020069static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
Gerlando Falauto45515162012-07-20 02:34:25 +000070{
Stefan Roese96c5f082014-10-22 12:13:13 +020071 struct sdram_addr_dec *base =
72 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Gerlando Falauto45515162012-07-20 02:34:25 +000073 /* Read current register value */
74 u32 reg = readl(&base->sdram_bank[bank].win_sz);
75
76 /* Clear window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020077 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
Gerlando Falauto45515162012-07-20 02:34:25 +000078
79 /* Set new window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020080 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
Gerlando Falauto45515162012-07-20 02:34:25 +000081
82 writel(reg, &base->sdram_bank[bank].win_sz);
83}
84
85/*
Stefan Roese96c5f082014-10-22 12:13:13 +020086 * mvebu_sdram_bs - reads SDRAM Bank size
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020087 */
Stefan Roese96c5f082014-10-22 12:13:13 +020088u32 mvebu_sdram_bs(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020089{
Stefan Roese96c5f082014-10-22 12:13:13 +020090 struct sdram_addr_dec *base =
91 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020092 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000093 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020094
95 if ((!enable) || (bank > BANK3))
96 return 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000097 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020098 result += 0x01000000;
99 return result;
100}
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530101
Stefan Roese96c5f082014-10-22 12:13:13 +0200102void mvebu_sdram_size_adjust(enum memory_bank bank)
Gerlando Falautob3168f42012-07-25 06:23:48 +0000103{
104 u32 size;
105
106 /* probe currently equipped RAM size */
Stefan Roese96c5f082014-10-22 12:13:13 +0200107 size = get_ram_size((void *)mvebu_sdram_bar(bank),
108 mvebu_sdram_bs(bank));
Gerlando Falautob3168f42012-07-25 06:23:48 +0000109
110 /* adjust SDRAM window size accordingly */
Stefan Roese96c5f082014-10-22 12:13:13 +0200111 mvebu_sdram_bs_set(bank, size);
Gerlando Falautob3168f42012-07-25 06:23:48 +0000112}
113
Stefan Roese81e33f42015-12-21 13:56:33 +0100114#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200115static u32 xor_ctrl_save;
116static u32 xor_base_save;
117static u32 xor_mask_save;
118
119static void mv_xor_init2(u32 cs)
120{
121 u32 reg, base, size, base2;
122 u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
123
124 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
125 SCRB_XOR_CHAN));
126 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
127 SCRB_XOR_WIN));
128 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
129 SCRB_XOR_WIN));
130
131 /* Enable Window x for each CS */
132 reg = 0x1;
133 reg |= (0x3 << 16);
134 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
135
136 base = 0;
137 size = mvebu_sdram_bs(cs) - 1;
138 if (size) {
139 base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
140 bank_attr[cs];
141 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
142 base2);
143
144 base += size + 1;
145 size = (size / (64 << 10)) << 16;
146 /* Window x - size - 256 MB */
147 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
148 }
149
150 mv_xor_hal_init(0);
151
152 return;
153}
154
155static void mv_xor_finish2(void)
156{
157 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
158 xor_ctrl_save);
159 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
160 xor_base_save);
161 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
162 xor_mask_save);
163}
164
165static void dram_ecc_scrubbing(void)
166{
167 int cs;
168 u32 size, temp;
169 u32 total_mem = 0;
170 u64 total;
171 u32 start_addr;
172
173 /*
174 * The DDR training code from the bin_hdr / SPL already
175 * scrubbed the DDR till 0x1000000. And the main U-Boot
176 * is loaded to an address < 0x1000000. So we need to
177 * skip this range to not re-scrub this area again.
178 */
179 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
180 temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
181 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
182
183 for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
Chris Packhamc3ab2742017-09-23 04:50:31 +1200184 size = mvebu_sdram_bs(cs);
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200185 if (size == 0)
186 continue;
187
Chris Packhamc3ab2742017-09-23 04:50:31 +1200188 total = (u64)size;
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200189 total_mem += (u32)(total / (1 << 30));
190 start_addr = 0;
191 mv_xor_init2(cs);
192
193 /* Skip first 16 MiB */
194 if (0 == cs) {
195 start_addr = 0x1000000;
196 size -= start_addr;
197 }
198
Chris Packhamc3ab2742017-09-23 04:50:31 +1200199 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200200 SCRUB_MAGIC, SCRUB_MAGIC);
201
202 /* Wait for previous transfer completion */
203 while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
204 ;
205
206 mv_xor_finish2();
207 }
208
209 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
210 temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
211 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
212}
213
214static int ecc_enabled(void)
215{
216 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
217 return 1;
218
219 return 0;
220}
Joshua Scott631407c2017-09-04 17:38:32 +1200221
222/* Return the width of the DRAM bus, or 0 for unknown. */
223static int bus_width(void)
224{
225 int full_width = 0;
226
227 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
228 full_width = 1;
229
230 switch (mvebu_soc_family()) {
231 case MVEBU_SOC_AXP:
232 return full_width ? 64 : 32;
233 break;
234 case MVEBU_SOC_A375:
235 case MVEBU_SOC_A38X:
236 case MVEBU_SOC_MSYS:
237 return full_width ? 32 : 16;
238 default:
239 return 0;
240 }
241}
242
243static int cycle_mode(void)
244{
245 int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
246
247 return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
248}
249
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200250#else
251static void dram_ecc_scrubbing(void)
252{
253}
254
255static int ecc_enabled(void)
256{
257 return 0;
258}
259#endif
260
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530261int dram_init(void)
262{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200263 u64 size = 0;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530264 int i;
265
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530266 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530267 /*
268 * It is assumed that all memory banks are consecutive
269 * and without gaps.
270 * If the gap is found, ram_size will be reported for
271 * consecutive memory only
272 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200273 if (mvebu_sdram_bar(i) != size)
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530274 break;
275
Stefan Roesed80cca22014-10-22 12:13:05 +0200276 /*
277 * Don't report more than 3GiB of SDRAM, otherwise there is no
278 * address space left for the internal registers etc.
279 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200280 size += mvebu_sdram_bs(i);
Stefan Roesea8483502018-10-22 14:21:17 +0200281 if (size > MVEBU_SDRAM_SIZE_MAX)
282 size = MVEBU_SDRAM_SIZE_MAX;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530283 }
Tanmay Upadhyay28e57102010-10-28 20:06:22 +0530284
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200285 if (ecc_enabled())
286 dram_ecc_scrubbing();
287
Stefan Roesea8b57a92015-08-10 15:11:27 +0200288 gd->ram_size = size;
289
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530290 return 0;
291}
292
293/*
294 * If this function is not defined here,
295 * board.c alters dram bank zero configuration defined above.
296 */
Simon Glass76b00ac2017-03-31 08:40:32 -0600297int dram_init_banksize(void)
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530298{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200299 u64 size = 0;
300 int i;
301
302 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
303 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
304 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
305
306 /* Clip the banksize to 1GiB if it exceeds the max size */
307 size += gd->bd->bi_dram[i].size;
Stefan Roesea8483502018-10-22 14:21:17 +0200308 if (size > MVEBU_SDRAM_SIZE_MAX)
Stefan Roesea8b57a92015-08-10 15:11:27 +0200309 mvebu_sdram_bs_set(i, 0x40000000);
310 }
Simon Glass76b00ac2017-03-31 08:40:32 -0600311
312 return 0;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530313}
Stefan Roese8a83c652015-08-03 13:15:31 +0200314
Stefan Roese81e33f42015-12-21 13:56:33 +0100315#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese8a83c652015-08-03 13:15:31 +0200316void board_add_ram_info(int use_default)
317{
Stefan Roesed718bf22015-12-21 12:36:40 +0100318 struct sar_freq_modes sar_freq;
Joshua Scott631407c2017-09-04 17:38:32 +1200319 int mode;
320 int width;
Stefan Roesed718bf22015-12-21 12:36:40 +0100321
322 get_sar_freq(&sar_freq);
323 printf(" (%d MHz, ", sar_freq.d_clk);
324
Joshua Scott631407c2017-09-04 17:38:32 +1200325 width = bus_width();
326 if (width)
327 printf("%d-bit, ", width);
328
329 mode = cycle_mode();
330 /* Mode 0 = Single cycle
331 * Mode 1 = Two cycles (2T)
332 * Mode 2 = Three cycles (3T)
333 */
334 if (mode == 1)
335 printf("2T, ");
336 if (mode == 2)
337 printf("3T, ");
338
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200339 if (ecc_enabled())
Stefan Roesed718bf22015-12-21 12:36:40 +0100340 printf("ECC");
Stefan Roese8a83c652015-08-03 13:15:31 +0200341 else
Stefan Roesed718bf22015-12-21 12:36:40 +0100342 printf("ECC not");
Stefan Roese8a83c652015-08-03 13:15:31 +0200343 printf(" enabled)");
344}
Stefan Roesed718bf22015-12-21 12:36:40 +0100345#endif