Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <config.h> |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 9 | #include <common.h> |
Simon Glass | 9b4a205 | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 10 | #include <init.h> |
Lei Wen | a7efd71 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/cpu.h> |
Stefan Roese | 3dc23f7 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 13 | #include <asm/arch/soc.h> |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 14 | |
Stefan Roese | 81e33f4 | 2015-12-21 13:56:33 +0100 | [diff] [blame] | 15 | #if defined(CONFIG_ARCH_MVEBU) |
| 16 | /* Use common XOR definitions for A3x and AXP */ |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 17 | #include "../../../drivers/ddr/marvell/axp/xor.h" |
| 18 | #include "../../../drivers/ddr/marvell/axp/xor_regs.h" |
Stefan Roese | 8a83c65 | 2015-08-03 13:15:31 +0200 | [diff] [blame] | 19 | #endif |
| 20 | |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 23 | struct sdram_bank { |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 24 | u32 win_bar; |
| 25 | u32 win_sz; |
| 26 | }; |
| 27 | |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 28 | struct sdram_addr_dec { |
| 29 | struct sdram_bank sdram_bank[4]; |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 30 | }; |
| 31 | |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 32 | #define REG_CPUCS_WIN_ENABLE (1 << 0) |
| 33 | #define REG_CPUCS_WIN_WR_PROTECT (1 << 1) |
| 34 | #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) |
| 35 | #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 36 | |
Stefan Roese | a848350 | 2018-10-22 14:21:17 +0200 | [diff] [blame] | 37 | #ifndef MVEBU_SDRAM_SIZE_MAX |
| 38 | #define MVEBU_SDRAM_SIZE_MAX 0xc0000000 |
| 39 | #endif |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 40 | |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 41 | #define SCRUB_MAGIC 0xbeefdead |
| 42 | |
| 43 | #define SCRB_XOR_UNIT 0 |
| 44 | #define SCRB_XOR_CHAN 1 |
| 45 | #define SCRB_XOR_WIN 0 |
| 46 | |
| 47 | #define XEBARX_BASE_OFFS 16 |
| 48 | |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 49 | /* |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 50 | * mvebu_sdram_bar - reads SDRAM Base Address Register |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 51 | */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 52 | u32 mvebu_sdram_bar(enum memory_bank bank) |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 53 | { |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 54 | struct sdram_addr_dec *base = |
| 55 | (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 56 | u32 result = 0; |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 57 | u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 58 | |
| 59 | if ((!enable) || (bank > BANK3)) |
| 60 | return 0; |
| 61 | |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 62 | result = readl(&base->sdram_bank[bank].win_bar); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 63 | return result; |
| 64 | } |
| 65 | |
| 66 | /* |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 67 | * mvebu_sdram_bs_set - writes SDRAM Bank size |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 68 | */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 69 | static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size) |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 70 | { |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 71 | struct sdram_addr_dec *base = |
| 72 | (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 73 | /* Read current register value */ |
| 74 | u32 reg = readl(&base->sdram_bank[bank].win_sz); |
| 75 | |
| 76 | /* Clear window size */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 77 | reg &= ~REG_CPUCS_WIN_SIZE(0xFF); |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 78 | |
| 79 | /* Set new window size */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 80 | reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24); |
Gerlando Falauto | 4551516 | 2012-07-20 02:34:25 +0000 | [diff] [blame] | 81 | |
| 82 | writel(reg, &base->sdram_bank[bank].win_sz); |
| 83 | } |
| 84 | |
| 85 | /* |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 86 | * mvebu_sdram_bs - reads SDRAM Bank size |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 87 | */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 88 | u32 mvebu_sdram_bs(enum memory_bank bank) |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 89 | { |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 90 | struct sdram_addr_dec *base = |
| 91 | (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 92 | u32 result = 0; |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 93 | u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 94 | |
| 95 | if ((!enable) || (bank > BANK3)) |
| 96 | return 0; |
Holger Brunck | cf37c5d | 2012-07-20 02:34:24 +0000 | [diff] [blame] | 97 | result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 98 | result += 0x01000000; |
| 99 | return result; |
| 100 | } |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 101 | |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 102 | void mvebu_sdram_size_adjust(enum memory_bank bank) |
Gerlando Falauto | b3168f4 | 2012-07-25 06:23:48 +0000 | [diff] [blame] | 103 | { |
| 104 | u32 size; |
| 105 | |
| 106 | /* probe currently equipped RAM size */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 107 | size = get_ram_size((void *)mvebu_sdram_bar(bank), |
| 108 | mvebu_sdram_bs(bank)); |
Gerlando Falauto | b3168f4 | 2012-07-25 06:23:48 +0000 | [diff] [blame] | 109 | |
| 110 | /* adjust SDRAM window size accordingly */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 111 | mvebu_sdram_bs_set(bank, size); |
Gerlando Falauto | b3168f4 | 2012-07-25 06:23:48 +0000 | [diff] [blame] | 112 | } |
| 113 | |
Stefan Roese | 81e33f4 | 2015-12-21 13:56:33 +0100 | [diff] [blame] | 114 | #if defined(CONFIG_ARCH_MVEBU) |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 115 | static u32 xor_ctrl_save; |
| 116 | static u32 xor_base_save; |
| 117 | static u32 xor_mask_save; |
| 118 | |
| 119 | static void mv_xor_init2(u32 cs) |
| 120 | { |
| 121 | u32 reg, base, size, base2; |
| 122 | u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 }; |
| 123 | |
| 124 | xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, |
| 125 | SCRB_XOR_CHAN)); |
| 126 | xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, |
| 127 | SCRB_XOR_WIN)); |
| 128 | xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, |
| 129 | SCRB_XOR_WIN)); |
| 130 | |
| 131 | /* Enable Window x for each CS */ |
| 132 | reg = 0x1; |
| 133 | reg |= (0x3 << 16); |
| 134 | reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg); |
| 135 | |
| 136 | base = 0; |
| 137 | size = mvebu_sdram_bs(cs) - 1; |
| 138 | if (size) { |
| 139 | base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) | |
| 140 | bank_attr[cs]; |
| 141 | reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), |
| 142 | base2); |
| 143 | |
| 144 | base += size + 1; |
| 145 | size = (size / (64 << 10)) << 16; |
| 146 | /* Window x - size - 256 MB */ |
| 147 | reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size); |
| 148 | } |
| 149 | |
| 150 | mv_xor_hal_init(0); |
| 151 | |
| 152 | return; |
| 153 | } |
| 154 | |
| 155 | static void mv_xor_finish2(void) |
| 156 | { |
| 157 | reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), |
| 158 | xor_ctrl_save); |
| 159 | reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), |
| 160 | xor_base_save); |
| 161 | reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), |
| 162 | xor_mask_save); |
| 163 | } |
| 164 | |
| 165 | static void dram_ecc_scrubbing(void) |
| 166 | { |
| 167 | int cs; |
| 168 | u32 size, temp; |
| 169 | u32 total_mem = 0; |
| 170 | u64 total; |
| 171 | u32 start_addr; |
| 172 | |
| 173 | /* |
| 174 | * The DDR training code from the bin_hdr / SPL already |
| 175 | * scrubbed the DDR till 0x1000000. And the main U-Boot |
| 176 | * is loaded to an address < 0x1000000. So we need to |
| 177 | * skip this range to not re-scrub this area again. |
| 178 | */ |
| 179 | temp = reg_read(REG_SDRAM_CONFIG_ADDR); |
| 180 | temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS); |
| 181 | reg_write(REG_SDRAM_CONFIG_ADDR, temp); |
| 182 | |
| 183 | for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) { |
Chris Packham | c3ab274 | 2017-09-23 04:50:31 +1200 | [diff] [blame] | 184 | size = mvebu_sdram_bs(cs); |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 185 | if (size == 0) |
| 186 | continue; |
| 187 | |
Chris Packham | c3ab274 | 2017-09-23 04:50:31 +1200 | [diff] [blame] | 188 | total = (u64)size; |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 189 | total_mem += (u32)(total / (1 << 30)); |
| 190 | start_addr = 0; |
| 191 | mv_xor_init2(cs); |
| 192 | |
| 193 | /* Skip first 16 MiB */ |
| 194 | if (0 == cs) { |
| 195 | start_addr = 0x1000000; |
| 196 | size -= start_addr; |
| 197 | } |
| 198 | |
Chris Packham | c3ab274 | 2017-09-23 04:50:31 +1200 | [diff] [blame] | 199 | mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1, |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 200 | SCRUB_MAGIC, SCRUB_MAGIC); |
| 201 | |
| 202 | /* Wait for previous transfer completion */ |
| 203 | while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE) |
| 204 | ; |
| 205 | |
| 206 | mv_xor_finish2(); |
| 207 | } |
| 208 | |
| 209 | temp = reg_read(REG_SDRAM_CONFIG_ADDR); |
| 210 | temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS); |
| 211 | reg_write(REG_SDRAM_CONFIG_ADDR, temp); |
| 212 | } |
| 213 | |
| 214 | static int ecc_enabled(void) |
| 215 | { |
| 216 | if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) |
| 217 | return 1; |
| 218 | |
| 219 | return 0; |
| 220 | } |
Joshua Scott | 631407c | 2017-09-04 17:38:32 +1200 | [diff] [blame] | 221 | |
| 222 | /* Return the width of the DRAM bus, or 0 for unknown. */ |
| 223 | static int bus_width(void) |
| 224 | { |
| 225 | int full_width = 0; |
| 226 | |
| 227 | if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) |
| 228 | full_width = 1; |
| 229 | |
| 230 | switch (mvebu_soc_family()) { |
| 231 | case MVEBU_SOC_AXP: |
| 232 | return full_width ? 64 : 32; |
| 233 | break; |
| 234 | case MVEBU_SOC_A375: |
| 235 | case MVEBU_SOC_A38X: |
| 236 | case MVEBU_SOC_MSYS: |
| 237 | return full_width ? 32 : 16; |
| 238 | default: |
| 239 | return 0; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | static int cycle_mode(void) |
| 244 | { |
| 245 | int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); |
| 246 | |
| 247 | return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK; |
| 248 | } |
| 249 | |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 250 | #else |
| 251 | static void dram_ecc_scrubbing(void) |
| 252 | { |
| 253 | } |
| 254 | |
| 255 | static int ecc_enabled(void) |
| 256 | { |
| 257 | return 0; |
| 258 | } |
| 259 | #endif |
| 260 | |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 261 | int dram_init(void) |
| 262 | { |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 263 | u64 size = 0; |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 264 | int i; |
| 265 | |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 266 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 267 | /* |
| 268 | * It is assumed that all memory banks are consecutive |
| 269 | * and without gaps. |
| 270 | * If the gap is found, ram_size will be reported for |
| 271 | * consecutive memory only |
| 272 | */ |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 273 | if (mvebu_sdram_bar(i) != size) |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 274 | break; |
| 275 | |
Stefan Roese | d80cca2 | 2014-10-22 12:13:05 +0200 | [diff] [blame] | 276 | /* |
| 277 | * Don't report more than 3GiB of SDRAM, otherwise there is no |
| 278 | * address space left for the internal registers etc. |
| 279 | */ |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 280 | size += mvebu_sdram_bs(i); |
Stefan Roese | a848350 | 2018-10-22 14:21:17 +0200 | [diff] [blame] | 281 | if (size > MVEBU_SDRAM_SIZE_MAX) |
| 282 | size = MVEBU_SDRAM_SIZE_MAX; |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 283 | } |
Tanmay Upadhyay | 28e5710 | 2010-10-28 20:06:22 +0530 | [diff] [blame] | 284 | |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 285 | if (ecc_enabled()) |
| 286 | dram_ecc_scrubbing(); |
| 287 | |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 288 | gd->ram_size = size; |
| 289 | |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * If this function is not defined here, |
| 295 | * board.c alters dram bank zero configuration defined above. |
| 296 | */ |
Simon Glass | 76b00ac | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 297 | int dram_init_banksize(void) |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 298 | { |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 299 | u64 size = 0; |
| 300 | int i; |
| 301 | |
| 302 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 303 | gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); |
| 304 | gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); |
| 305 | |
| 306 | /* Clip the banksize to 1GiB if it exceeds the max size */ |
| 307 | size += gd->bd->bi_dram[i].size; |
Stefan Roese | a848350 | 2018-10-22 14:21:17 +0200 | [diff] [blame] | 308 | if (size > MVEBU_SDRAM_SIZE_MAX) |
Stefan Roese | a8b57a9 | 2015-08-10 15:11:27 +0200 | [diff] [blame] | 309 | mvebu_sdram_bs_set(i, 0x40000000); |
| 310 | } |
Simon Glass | 76b00ac | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 311 | |
| 312 | return 0; |
Prafulla Wadaskar | beeb258 | 2010-09-30 19:33:19 +0530 | [diff] [blame] | 313 | } |
Stefan Roese | 8a83c65 | 2015-08-03 13:15:31 +0200 | [diff] [blame] | 314 | |
Stefan Roese | 81e33f4 | 2015-12-21 13:56:33 +0100 | [diff] [blame] | 315 | #if defined(CONFIG_ARCH_MVEBU) |
Stefan Roese | 8a83c65 | 2015-08-03 13:15:31 +0200 | [diff] [blame] | 316 | void board_add_ram_info(int use_default) |
| 317 | { |
Stefan Roese | d718bf2 | 2015-12-21 12:36:40 +0100 | [diff] [blame] | 318 | struct sar_freq_modes sar_freq; |
Joshua Scott | 631407c | 2017-09-04 17:38:32 +1200 | [diff] [blame] | 319 | int mode; |
| 320 | int width; |
Stefan Roese | d718bf2 | 2015-12-21 12:36:40 +0100 | [diff] [blame] | 321 | |
| 322 | get_sar_freq(&sar_freq); |
| 323 | printf(" (%d MHz, ", sar_freq.d_clk); |
| 324 | |
Joshua Scott | 631407c | 2017-09-04 17:38:32 +1200 | [diff] [blame] | 325 | width = bus_width(); |
| 326 | if (width) |
| 327 | printf("%d-bit, ", width); |
| 328 | |
| 329 | mode = cycle_mode(); |
| 330 | /* Mode 0 = Single cycle |
| 331 | * Mode 1 = Two cycles (2T) |
| 332 | * Mode 2 = Three cycles (3T) |
| 333 | */ |
| 334 | if (mode == 1) |
| 335 | printf("2T, "); |
| 336 | if (mode == 2) |
| 337 | printf("3T, "); |
| 338 | |
Stefan Roese | 0ceb2da | 2015-08-06 14:43:13 +0200 | [diff] [blame] | 339 | if (ecc_enabled()) |
Stefan Roese | d718bf2 | 2015-12-21 12:36:40 +0100 | [diff] [blame] | 340 | printf("ECC"); |
Stefan Roese | 8a83c65 | 2015-08-03 13:15:31 +0200 | [diff] [blame] | 341 | else |
Stefan Roese | d718bf2 | 2015-12-21 12:36:40 +0100 | [diff] [blame] | 342 | printf("ECC not"); |
Stefan Roese | 8a83c65 | 2015-08-03 13:15:31 +0200 | [diff] [blame] | 343 | printf(" enabled)"); |
| 344 | } |
Stefan Roese | d718bf2 | 2015-12-21 12:36:40 +0100 | [diff] [blame] | 345 | #endif |