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wdenk38635852002-08-27 05:55:31 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
d4f5c722005-08-12 21:16:13 +020025/*
26 * Support for read and write access to EEPROM like memory devices. This
27 * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
28 * FRAM devices read and write data at bus speed. In particular, there is no
29 * write delay. Also, there is no limit imposed on the numer of bytes that can
30 * be transferred with a single read or write.
Wolfgang Denk6617aae2005-08-19 00:46:54 +020031 *
d4f5c722005-08-12 21:16:13 +020032 * Use the following configuration options to ensure no unneeded performance
33 * degradation (typical for EEPROM) is incured for FRAM memory:
Wolfgang Denk6617aae2005-08-19 00:46:54 +020034 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035 * #define CONFIG_SYS_I2C_FRAM
36 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
d4f5c722005-08-12 21:16:13 +020037 *
38 */
39
wdenk38635852002-08-27 05:55:31 +000040#include <common.h>
41#include <config.h>
42#include <command.h>
43#include <i2c.h>
44
wdenk38635852002-08-27 05:55:31 +000045extern void eeprom_init (void);
46extern int eeprom_read (unsigned dev_addr, unsigned offset,
47 uchar *buffer, unsigned cnt);
48extern int eeprom_write (unsigned dev_addr, unsigned offset,
49 uchar *buffer, unsigned cnt);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roese98f4a3d2005-09-22 09:04:17 +020051extern int eeprom_write_enable (unsigned dev_addr, int state);
52#endif
wdenk38635852002-08-27 05:55:31 +000053
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#if defined(CONFIG_SYS_EEPROM_X40430)
wdenk38635852002-08-27 05:55:31 +000056 /* Maximum number of times to poll for acknowledge after write */
57#define MAX_ACKNOWLEDGE_POLLS 10
58#endif
59
60/* ------------------------------------------------------------------------- */
61
Jon Loeligerbaa26db2007-07-08 17:51:39 -050062#if defined(CONFIG_CMD_EEPROM)
wdenk38635852002-08-27 05:55:31 +000063int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
64{
65 const char *const fmt =
66 "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
67
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
wdenk38635852002-08-27 05:55:31 +000069 if (argc == 6) {
70 ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
71 ulong addr = simple_strtoul (argv[3], NULL, 16);
72 ulong off = simple_strtoul (argv[4], NULL, 16);
73 ulong cnt = simple_strtoul (argv[5], NULL, 16);
74#else
75 if (argc == 5) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
wdenk38635852002-08-27 05:55:31 +000077 ulong addr = simple_strtoul (argv[2], NULL, 16);
78 ulong off = simple_strtoul (argv[3], NULL, 16);
79 ulong cnt = simple_strtoul (argv[4], NULL, 16);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
wdenk38635852002-08-27 05:55:31 +000081
82# ifndef CONFIG_SPI
83 eeprom_init ();
84# endif /* !CONFIG_SPI */
85
86 if (strcmp (argv[1], "read") == 0) {
87 int rcode;
88
89 printf (fmt, dev_addr, argv[1], addr, off, cnt);
90
91 rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
92
wdenk4b9206e2004-03-23 22:14:11 +000093 puts ("done\n");
wdenk38635852002-08-27 05:55:31 +000094 return rcode;
95 } else if (strcmp (argv[1], "write") == 0) {
96 int rcode;
97
98 printf (fmt, dev_addr, argv[1], addr, off, cnt);
99
100 rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
101
wdenk4b9206e2004-03-23 22:14:11 +0000102 puts ("done\n");
wdenk38635852002-08-27 05:55:31 +0000103 return rcode;
104 }
105 }
106
Peter Tyser62c3ae72009-01-27 18:03:10 -0600107 cmd_usage(cmdtp);
wdenk38635852002-08-27 05:55:31 +0000108 return 1;
109}
Jon Loeliger90253172007-07-10 11:02:44 -0500110#endif
wdenk38635852002-08-27 05:55:31 +0000111
112/*-----------------------------------------------------------------------
113 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
wdenk38635852002-08-27 05:55:31 +0000115 * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
116 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
wdenk38635852002-08-27 05:55:31 +0000118 * 0x00000nxx for EEPROM address selectors and page number at n.
119 */
120
wdenk38635852002-08-27 05:55:31 +0000121#ifndef CONFIG_SPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
123#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
wdenk38635852002-08-27 05:55:31 +0000124#endif
125#endif
126
127int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
128{
129 unsigned end = offset + cnt;
130 unsigned blk_off;
131 int rcode = 0;
132
133 /* Read data until done or would cross a page boundary.
134 * We must write the address again when changing pages
135 * because the next page may be in a different device.
136 */
137 while (offset < end) {
d4f5c722005-08-12 21:16:13 +0200138 unsigned alen, len;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c722005-08-12 21:16:13 +0200140 unsigned maxlen;
141#endif
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
wdenk38635852002-08-27 05:55:31 +0000144 uchar addr[2];
145
146 blk_off = offset & 0xFF; /* block offset */
147
148 addr[0] = offset >> 8; /* block number */
149 addr[1] = blk_off; /* block offset */
150 alen = 2;
151#else
152 uchar addr[3];
153
154 blk_off = offset & 0xFF; /* block offset */
155
156 addr[0] = offset >> 16; /* block number */
157 addr[1] = offset >> 8; /* upper address octet */
158 addr[2] = blk_off; /* lower address octet */
159 alen = 3;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
wdenk38635852002-08-27 05:55:31 +0000161
162 addr[0] |= dev_addr; /* insert device address */
163
d4f5c722005-08-12 21:16:13 +0200164 len = end - offset;
165
166 /*
167 * For a FRAM device there is no limit on the number of the
168 * bytes that can be ccessed with the single read or write
169 * operation.
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#if !defined(CONFIG_SYS_I2C_FRAM)
wdenk38635852002-08-27 05:55:31 +0000172 maxlen = 0x100 - blk_off;
173 if (maxlen > I2C_RXTX_LEN)
174 maxlen = I2C_RXTX_LEN;
wdenk38635852002-08-27 05:55:31 +0000175 if (len > maxlen)
176 len = maxlen;
d4f5c722005-08-12 21:16:13 +0200177#endif
178
wdenk38635852002-08-27 05:55:31 +0000179#ifdef CONFIG_SPI
180 spi_read (addr, alen, buffer, len);
181#else
182 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
183 rcode = 1;
184#endif
185 buffer += len;
186 offset += len;
187 }
d4f5c722005-08-12 21:16:13 +0200188
wdenk38635852002-08-27 05:55:31 +0000189 return rcode;
190}
191
192/*-----------------------------------------------------------------------
193 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
wdenk38635852002-08-27 05:55:31 +0000195 * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
196 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
wdenk38635852002-08-27 05:55:31 +0000198 * 0x00000nxx for EEPROM address selectors and page number at n.
199 */
200
201int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
202{
203 unsigned end = offset + cnt;
204 unsigned blk_off;
205 int rcode = 0;
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#if defined(CONFIG_SYS_EEPROM_X40430)
wdenk38635852002-08-27 05:55:31 +0000208 uchar contr_r_addr[2];
209 uchar addr_void[2];
210 uchar contr_reg[2];
211 uchar ctrl_reg_v;
212 int i;
213#endif
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200216 eeprom_write_enable (dev_addr,1);
217#endif
wdenk38635852002-08-27 05:55:31 +0000218 /* Write data until done or would cross a write page boundary.
219 * We must write the address again when changing pages
220 * because the address counter only increments within a page.
221 */
222
223 while (offset < end) {
d4f5c722005-08-12 21:16:13 +0200224 unsigned alen, len;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c722005-08-12 21:16:13 +0200226 unsigned maxlen;
227#endif
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
wdenk38635852002-08-27 05:55:31 +0000230 uchar addr[2];
231
232 blk_off = offset & 0xFF; /* block offset */
233
234 addr[0] = offset >> 8; /* block number */
235 addr[1] = blk_off; /* block offset */
236 alen = 2;
237#else
238 uchar addr[3];
239
240 blk_off = offset & 0xFF; /* block offset */
241
242 addr[0] = offset >> 16; /* block number */
243 addr[1] = offset >> 8; /* upper address octet */
244 addr[2] = blk_off; /* lower address octet */
245 alen = 3;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
wdenk38635852002-08-27 05:55:31 +0000247
248 addr[0] |= dev_addr; /* insert device address */
249
d4f5c722005-08-12 21:16:13 +0200250 len = end - offset;
251
252 /*
253 * For a FRAM device there is no limit on the number of the
254 * bytes that can be ccessed with the single read or write
255 * operation.
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c722005-08-12 21:16:13 +0200258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
wdenk38635852002-08-27 05:55:31 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
wdenk38635852002-08-27 05:55:31 +0000262#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
263
264 maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
265#else
266 maxlen = 0x100 - blk_off;
267#endif
268 if (maxlen > I2C_RXTX_LEN)
269 maxlen = I2C_RXTX_LEN;
270
wdenk38635852002-08-27 05:55:31 +0000271 if (len > maxlen)
272 len = maxlen;
d4f5c722005-08-12 21:16:13 +0200273#endif
274
wdenk38635852002-08-27 05:55:31 +0000275#ifdef CONFIG_SPI
276 spi_write (addr, alen, buffer, len);
277#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#if defined(CONFIG_SYS_EEPROM_X40430)
wdenk38635852002-08-27 05:55:31 +0000279 /* Get the value of the control register.
280 * Set current address (internal pointer in the x40430)
281 * to 0x1ff.
282 */
283 contr_r_addr[0] = 9;
284 contr_r_addr[1] = 0xff;
285 addr_void[0] = 0;
286 addr_void[1] = addr[1];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
288 contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
289 addr_void[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
wdenk38635852002-08-27 05:55:31 +0000290#endif
291 contr_reg[0] = 0xff;
292 if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
293 rcode = 1;
294 }
295 ctrl_reg_v = contr_reg[0];
296
297 /* Are any of the eeprom blocks write protected?
298 */
299 if (ctrl_reg_v & 0x18) {
300 ctrl_reg_v &= ~0x18; /* reset block protect bits */
301 ctrl_reg_v |= 0x02; /* set write enable latch */
302 ctrl_reg_v &= ~0x04; /* clear RWEL */
303
304 /* Set write enable latch.
305 */
306 contr_reg[0] = 0x02;
307 if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
308 rcode = 1;
309 }
310
311 /* Set register write enable latch.
312 */
313 contr_reg[0] = 0x06;
314 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
315 rcode = 1;
316 }
317
318 /* Modify ctrl register.
319 */
320 contr_reg[0] = ctrl_reg_v;
321 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
322 rcode = 1;
323 }
324
325 /* The write (above) is an operation on NV memory.
326 * These can take some time (~5ms), and the device
327 * will not respond to further I2C messages till
328 * it's completed the write.
329 * So poll device for an I2C acknowledge.
330 * When we get one we know we can continue with other
331 * operations.
332 */
333 contr_reg[0] = 0;
334 for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
wdenkaacf9a42003-01-17 16:27:01 +0000335 if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
wdenk38635852002-08-27 05:55:31 +0000336 break; /* got ack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
338 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
wdenk38635852002-08-27 05:55:31 +0000339#endif
340 }
341 if (i == MAX_ACKNOWLEDGE_POLLS) {
wdenk4b9206e2004-03-23 22:14:11 +0000342 puts ("EEPROM poll acknowledge failed\n");
wdenk38635852002-08-27 05:55:31 +0000343 rcode = 1;
344 }
345 }
346
347 /* Is the write enable latch on?.
348 */
349 else if (!(ctrl_reg_v & 0x02)) {
350 /* Set write enable latch.
351 */
352 contr_reg[0] = 0x02;
353 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
354 rcode = 1;
355 }
356 }
357 /* Write is enabled ... now write eeprom value.
358 */
359#endif
360 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
361 rcode = 1;
362
363#endif
364 buffer += len;
365 offset += len;
366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
368 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
wdenk38635852002-08-27 05:55:31 +0000369#endif
370 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200372 eeprom_write_enable (dev_addr,0);
373#endif
wdenk38635852002-08-27 05:55:31 +0000374 return rcode;
375}
376
wdenk6dd652f2003-06-19 23:40:20 +0000377#ifndef CONFIG_SPI
378int
379eeprom_probe (unsigned dev_addr, unsigned offset)
380{
381 unsigned char chip;
382
383 /* Probe the chip address
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
wdenk6dd652f2003-06-19 23:40:20 +0000386 chip = offset >> 8; /* block number */
387#else
388 chip = offset >> 16; /* block number */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
wdenk6dd652f2003-06-19 23:40:20 +0000390
391 chip |= dev_addr; /* insert device address */
392
393 return (i2c_probe (chip));
394}
395#endif
396
wdenk38635852002-08-27 05:55:31 +0000397/*-----------------------------------------------------------------------
398 * Set default values
399 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#ifndef CONFIG_SYS_I2C_SPEED
401#define CONFIG_SYS_I2C_SPEED 50000
wdenk38635852002-08-27 05:55:31 +0000402#endif
403
wdenk38635852002-08-27 05:55:31 +0000404void eeprom_init (void)
405{
406#if defined(CONFIG_SPI)
407 spi_init_f ();
408#endif
409#if defined(CONFIG_HARD_I2C) || \
410 defined(CONFIG_SOFT_I2C)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenk38635852002-08-27 05:55:31 +0000412#endif
413}
414/*-----------------------------------------------------------------------
415 */
Jon Loeliger90253172007-07-10 11:02:44 -0500416
wdenk8bde7f72003-06-27 21:31:46 +0000417/***************************************************/
418
Jon Loeligerbaa26db2007-07-08 17:51:39 -0500419#if defined(CONFIG_CMD_EEPROM)
wdenk8bde7f72003-06-27 21:31:46 +0000420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
wdenk0d498392003-07-01 21:06:45 +0000422U_BOOT_CMD(
423 eeprom, 6, 1, do_eeprom,
Peter Tyser2fb26042009-01-27 18:03:12 -0600424 "EEPROM sub-system",
wdenk8bde7f72003-06-27 21:31:46 +0000425 "read devaddr addr off cnt\n"
426 "eeprom write devaddr addr off cnt\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200427 " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
wdenk8bde7f72003-06-27 21:31:46 +0000428);
429#else /* One EEPROM */
wdenk0d498392003-07-01 21:06:45 +0000430U_BOOT_CMD(
431 eeprom, 5, 1, do_eeprom,
Peter Tyser2fb26042009-01-27 18:03:12 -0600432 "EEPROM sub-system",
wdenk8bde7f72003-06-27 21:31:46 +0000433 "read addr off cnt\n"
434 "eeprom write addr off cnt\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200435 " - read/write `cnt' bytes at EEPROM offset `off'"
wdenk8bde7f72003-06-27 21:31:46 +0000436);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
wdenk8bde7f72003-06-27 21:31:46 +0000438
Jon Loeliger90253172007-07-10 11:02:44 -0500439#endif