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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a17824c749aac3df0bbb528bb5d33af68296b0b1 / . / include / asm-blackfin / arch-bf537 / cplbtab.h
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Aubrey Li26bf7de2007-03-19 01:24:52 +0800[diff] [blame]1/*This file is subject to the terms and conditions of the GNU General Public
2 * License.
3 *
4 * Blackfin BF533/2.6 support : LG Soft India
5 * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
6 * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
7 * shouldn't be victimized. cplbmgr.S search logic is corrected
8 * to findout the appropriate victim.
9 * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
10 * : LG Soft India
11 */
12#include <config.h>
13
14#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
15#define __ARCH_BFINNOMMU_CPLBTAB_H
16
17/*
18 * ICPLB TABLE
19 */
20
21.data
22/* This table is configurable */
23 .align 4;
24
25/* Data Attibutes*/
26
27#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
28#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
29#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
30#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
31
32/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
33
34#define ANOMALY_05000158 0x200
35#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
36#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
37#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
38#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
39#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
40#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
41
42#else /*Write Through */
43#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
44#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
45#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
46#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
47#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
48#endif
49
50.align 4;
51.global _ipdt_table _ipdt_table:.byte4 0x00000000;
52.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
53.byte4 0x00400000;
54.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
55.byte4 0x00800000;
56.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
57.byte4 0x00C00000;
58.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
59.byte4 0x01000000;
60.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
61.byte4 0x01400000;
62.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
63.byte4 0x01800000;
64.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
65.byte4 0x01C00000;
66.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
67.byte4 0x02000000;
68.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
69.byte4 0x02400000;
70.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
71.byte4 0x02800000;
72.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
73.byte4 0x02C00000;
74.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
75.byte4 0x03000000;
76.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
77.byte4 0x03400000;
78.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
79.byte4 0x03800000;
80.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
81.byte4 0x03C00000;
82.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
83.byte4 0x20000000;
84.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
85
86.byte4 0xffffffff; /* end of section - termination */
87
88/*
89 * PAGE DESCRIPTOR TABLE
90 *
91 */
92
93/*
94 * Till here we are discussing about the static memory management model.
95 * However, the operating envoronments commonly define more CPLB
96 * descriptors to cover the entire addressable memory than will fit into
97 * the available on-chip 16 CPLB MMRs. When this happens, the below table
98 * will be used which will hold all the potentially required CPLB descriptors
99 *
100 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
101 */
102.global _dpdt_table _dpdt_table:.byte4 0x00000000;
103.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
104.byte4 0x00400000;
105.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
106.byte4 0x00800000;
107.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
108.byte4 0x00C00000;
109.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
110.byte4 0x01000000;
111.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
112.byte4 0x01400000;
113.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
114.byte4 0x01800000;
115.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
116.byte4 0x01C00000;
117.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
118.byte4 0x02000000;
119.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
120.byte4 0x02400000;
121.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
122.byte4 0x02800000;
123.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
124.byte4 0x02C00000;
125.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
126.byte4 0x03000000;
127.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
128.byte4 0x03400000;
129.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
130.byte4 0x03800000;
131.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
132.byte4 0x03C00000;
133.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
134.byte4 0x20000000;
135.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
136
137#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
138.byte4 0xFF800000;
139.byte4(L1_DMEMORY);
140.byte4 0xFF801000;
141.byte4(L1_DMEMORY);
142.byte4 0xFF802000;
143.byte4(L1_DMEMORY);
144.byte4 0xFF803000;
145.byte4(L1_DMEMORY);
146#endif
147.byte4 0xFF804000;
148.byte4(L1_DMEMORY);
149.byte4 0xFF805000;
150.byte4(L1_DMEMORY);
151.byte4 0xFF806000;
152.byte4(L1_DMEMORY);
153.byte4 0xFF807000;
154.byte4(L1_DMEMORY);
155#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
156.byte4 0xFF900000;
157.byte4(L1_DMEMORY);
158.byte4 0xFF901000;
159.byte4(L1_DMEMORY);
160.byte4 0xFF902000;
161.byte4(L1_DMEMORY);
162.byte4 0xFF903000;
163.byte4(L1_DMEMORY);
164#endif
165.byte4 0xFF904000;
166.byte4(L1_DMEMORY);
167.byte4 0xFF905000;
168.byte4(L1_DMEMORY);
169.byte4 0xFF906000;
170.byte4(L1_DMEMORY);
171.byte4 0xFF907000;
172.byte4(L1_DMEMORY);
173
174.byte4 0xFFB00000;
175.byte4(L1_DMEMORY);
176
177.byte4 0xffffffff; /*end of section - termination */
178
179#ifdef CONFIG_CPLB_INFO
180.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
181_ipdt_swapcount_table:
182.byte4 0x00000000;
183.byte4 0x00000000;
184.byte4 0x00000000;
185.byte4 0x00000000;
186.byte4 0x00000000;
187.byte4 0x00000000;
188.byte4 0x00000000;
189.byte4 0x00000000;
190.byte4 0x00000000;
191.byte4 0x00000000; /* 10 */
192.byte4 0x00000000;
193.byte4 0x00000000;
194.byte4 0x00000000;
195.byte4 0x00000000;
196.byte4 0x00000000;
197.byte4 0x00000000;
198.byte4 0x00000000;
199.byte4 0x00000000;
200.byte4 0x00000000;
201.byte4 0x00000000; /* 20 */
202.byte4 0x00000000;
203.byte4 0x00000000;
204.byte4 0x00000000;
205.byte4 0x00000000;
206.byte4 0x00000000;
207.byte4 0x00000000;
208.byte4 0x00000000;
209.byte4 0x00000000;
210.byte4 0x00000000;
211.byte4 0x00000000; /* 30 */
212.byte4 0x00000000;
213.byte4 0x00000000;
214.byte4 0x00000000;
215.byte4 0x00000000;
216.byte4 0x00000000;
217.byte4 0x00000000;
218.byte4 0x00000000;
219.byte4 0x00000000;
220.byte4 0x00000000;
221.byte4 0x00000000; /* 40 */
222.byte4 0x00000000;
223.byte4 0x00000000;
224.byte4 0x00000000;
225.byte4 0x00000000;
226.byte4 0x00000000;
227.byte4 0x00000000;
228.byte4 0x00000000;
229.byte4 0x00000000;
230.byte4 0x00000000;
231.byte4 0x00000000; /* 50 */
232.byte4 0x00000000;
233.byte4 0x00000000;
234.byte4 0x00000000;
235.byte4 0x00000000;
236.byte4 0x00000000;
237.byte4 0x00000000;
238.byte4 0x00000000;
239.byte4 0x00000000;
240.byte4 0x00000000;
241.byte4 0x00000000; /* 60 */
242.byte4 0x00000000;
243.byte4 0x00000000;
244.byte4 0x00000000;
245.byte4 0x00000000;
246.byte4 0x00000000;
247.byte4 0x00000000;
248.byte4 0x00000000;
249.byte4 0x00000000;
250.byte4 0x00000000;
251.byte4 0x00000000; /* 70 */
252.byte4 0x00000000;
253.byte4 0x00000000;
254.byte4 0x00000000;
255.byte4 0x00000000;
256.byte4 0x00000000;
257.byte4 0x00000000;
258.byte4 0x00000000;
259.byte4 0x00000000;
260.byte4 0x00000000;
261.byte4 0x00000000; /* 80 */
262.byte4 0x00000000;
263.byte4 0x00000000;
264.byte4 0x00000000;
265.byte4 0x00000000;
266.byte4 0x00000000;
267.byte4 0x00000000;
268.byte4 0x00000000;
269.byte4 0x00000000;
270.byte4 0x00000000;
271.byte4 0x00000000; /* 90 */
272.byte4 0x00000000;
273.byte4 0x00000000;
274.byte4 0x00000000;
275.byte4 0x00000000;
276.byte4 0x00000000;
277.byte4 0x00000000;
278.byte4 0x00000000;
279.byte4 0x00000000;
280.byte4 0x00000000;
281.byte4 0x00000000; /* 100 */
282
283.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
284_dpdt_swapcount_table:
285.byte4 0x00000000;
286.byte4 0x00000000;
287.byte4 0x00000000;
288.byte4 0x00000000;
289.byte4 0x00000000;
290.byte4 0x00000000;
291.byte4 0x00000000;
292.byte4 0x00000000;
293.byte4 0x00000000;
294.byte4 0x00000000; /* 10 */
295.byte4 0x00000000;
296.byte4 0x00000000;
297.byte4 0x00000000;
298.byte4 0x00000000;
299.byte4 0x00000000;
300.byte4 0x00000000;
301.byte4 0x00000000;
302.byte4 0x00000000;
303.byte4 0x00000000;
304.byte4 0x00000000; /* 20 */
305.byte4 0x00000000;
306.byte4 0x00000000;
307.byte4 0x00000000;
308.byte4 0x00000000;
309.byte4 0x00000000;
310.byte4 0x00000000;
311.byte4 0x00000000;
312.byte4 0x00000000;
313.byte4 0x00000000;
314.byte4 0x00000000; /* 30 */
315.byte4 0x00000000;
316.byte4 0x00000000;
317.byte4 0x00000000;
318.byte4 0x00000000;
319.byte4 0x00000000;
320.byte4 0x00000000;
321.byte4 0x00000000;
322.byte4 0x00000000;
323.byte4 0x00000000;
324.byte4 0x00000000; /* 40 */
325.byte4 0x00000000;
326.byte4 0x00000000;
327.byte4 0x00000000;
328.byte4 0x00000000;
329.byte4 0x00000000;
330.byte4 0x00000000;
331.byte4 0x00000000;
332.byte4 0x00000000;
333.byte4 0x00000000;
334.byte4 0x00000000; /* 50 */
335.byte4 0x00000000;
336.byte4 0x00000000;
337.byte4 0x00000000;
338.byte4 0x00000000;
339.byte4 0x00000000;
340.byte4 0x00000000;
341.byte4 0x00000000;
342.byte4 0x00000000;
343.byte4 0x00000000;
344.byte4 0x00000000; /* 60 */
345.byte4 0x00000000;
346.byte4 0x00000000;
347.byte4 0x00000000;
348.byte4 0x00000000;
349.byte4 0x00000000;
350.byte4 0x00000000;
351.byte4 0x00000000;
352.byte4 0x00000000;
353.byte4 0x00000000;
354.byte4 0x00000000; /* 70 */
355.byte4 0x00000000;
356.byte4 0x00000000;
357.byte4 0x00000000;
358.byte4 0x00000000;
359.byte4 0x00000000;
360.byte4 0x00000000;
361.byte4 0x00000000;
362.byte4 0x00000000;
363.byte4 0x00000000;
364.byte4 0x00000000; /* 80 */
365.byte4 0x00000000;
366.byte4 0x00000000;
367.byte4 0x00000000;
368.byte4 0x00000000;
369.byte4 0x00000000;
370.byte4 0x00000000;
371.byte4 0x00000000;
372.byte4 0x00000000;
373.byte4 0x00000000;
374.byte4 0x00000000; /* 80 */
375.byte4 0x00000000;
376.byte4 0x00000000;
377.byte4 0x00000000;
378.byte4 0x00000000;
379.byte4 0x00000000;
380.byte4 0x00000000;
381.byte4 0x00000000;
382.byte4 0x00000000;
383.byte4 0x00000000;
384.byte4 0x00000000; /* 100 */
385.byte4 0x00000000;
386.byte4 0x00000000;
387.byte4 0x00000000;
388.byte4 0x00000000;
389.byte4 0x00000000;
390.byte4 0x00000000;
391.byte4 0x00000000;
392.byte4 0x00000000;
393.byte4 0x00000000;
394.byte4 0x00000000; /* 110 */
395.byte4 0x00000000;
396.byte4 0x00000000;
397.byte4 0x00000000;
398.byte4 0x00000000;
399.byte4 0x00000000;
400.byte4 0x00000000;
401.byte4 0x00000000;
402.byte4 0x00000000;
403.byte4 0x00000000;
404.byte4 0x00000000; /* 120 */
405
406#endif
407
408#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/