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wdenkba91e262005-05-30 23:55:42 +00001/*
2 * (C) Copyright 2004
3 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
4 *
5 * Support for the Elmeg VoVPN Gateway Module
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/* define cpu used */
27#define CONFIG_MPC8272 1
28
29/* define busmode: 8260 */
30#undef CONFIG_BUSMODE_60x
31
32/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
33#ifdef CONFIG_CLKIN_66MHz
34#define CONFIG_8260_CLKIN 66666666 /* in Hz */
35#else
36#define CONFIG_8260_CLKIN 100000000 /* in Hz */
37#endif
38
39/* call board_early_init_f */
40#define CONFIG_BOARD_EARLY_INIT_F 1
41
42/* have misc_init_r() function */
43#define CONFIG_MISC_INIT_R 1
44
45/* have reset_phy_r() function */
46#define CONFIG_RESET_PHY_R 1
47
48/* have special reset function */
49#define CONFIG_HAVE_OWN_RESET 1
50
51/* allow serial and ethaddr to be overwritten */
52#define CONFIG_ENV_OVERWRITE
53
54/* watchdog disabled */
55#undef CONFIG_WATCHDOG
56
57/* include support for bzip2 compressed images */
58#undef CONFIG_BZIP2
59
60/* status led */
61#undef CONFIG_STATUS_LED /* XXX jse */
62
63/* vendor parameter protection */
64#define CONFIG_ENV_OVERWRITE
65
66/*
67 * select serial console configuration
68 *
69 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
70 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
71 * for SCC).
72 */
73#define CONFIG_CONS_ON_SMC
74#undef CONFIG_CONS_ON_SCC
75#undef CONFIG_CONS_NONE
76#define CONFIG_CONS_INDEX 1
77
78/* serial port default baudrate */
79#define CONFIG_BAUDRATE 115200
80
81/* echo on for serial download */
82#define CONFIG_LOADS_ECHO 1
83
84/* don't allow baudrate change */
85#undef CFG_LOADS_BAUD_CHANGE
86
87/* supported baudrates */
88#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89
90/*
91 * select ethernet configuration
92 *
93 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
94 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
95 * for FCC)
96 *
97 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050098 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkba91e262005-05-30 23:55:42 +000099 */
100#undef CONFIG_ETHER_ON_SCC
101#define CONFIG_ETHER_ON_FCC
102#undef CONFIG_ETHER_NONE
103
104#ifdef CONFIG_ETHER_ON_FCC
105
106/* which SCC/FCC channel for ethernet */
107#define CONFIG_ETHER_INDEX 1
108
109/* Marvell Switch SMI base addr */
110#define CFG_PHY_ADDR 0x10
111
112/* FCC1 RMII REFCLK is CLK10 */
113#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
114#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
115
116/* BDs and buffers on 60x bus */
117#define CFG_CPMFCR_RAMTYPE 0
118
119/* Local Protect, Full duplex, Flowcontrol, RMII */
120#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
121 FCC_PSMR_FCE|FCC_PSMR_RMII)
122
123/* bit-bang MII PHY management */
124#define CONFIG_BITBANGMII
125
126#define MDIO_PORT 1 /* Port B */
127#define CFG_MDIO_PIN 0x00002000 /* PB18 */
128#define CFG_MDC_PIN 0x00001000 /* PB19 */
129#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
130#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
131#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
132#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
133 else iop->pdat &= ~CFG_MDIO_PIN
134#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
135 else iop->pdat &= ~CFG_MDC_PIN
136#define MIIDELAY udelay(1)
137
138#endif
139
Jon Loeligera5562902007-07-08 15:31:57 -0500140/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500141 * BOOTP options
142 */
143#define CONFIG_BOOTP_BOOTFILESIZE
144#define CONFIG_BOOTP_BOOTPATH
145#define CONFIG_BOOTP_GATEWAY
146#define CONFIG_BOOTP_HOSTNAME
147
148
149/*
Jon Loeligera5562902007-07-08 15:31:57 -0500150 * Command line configuration.
151 */
wdenkba91e262005-05-30 23:55:42 +0000152
Jon Loeligera5562902007-07-08 15:31:57 -0500153#define CONFIG_CMD_AUTOSCRIPT
154#define CONFIG_CMD_BDI
155#define CONFIG_CMD_CONSOLE
156#define CONFIG_CMD_ECHO
157#define CONFIG_CMD_ENV
158#define CONFIG_CMD_FLASH
159#define CONFIG_CMD_IMI
160#define CONFIG_CMD_IMLS
161#define CONFIG_CMD_LOADB
162#define CONFIG_CMD_MEMORY
163#define CONFIG_CMD_MISC
164#define CONFIG_CMD_NET
165#define CONFIG_CMD_PING
166#define CONFIG_CMD_RUN
167
wdenkba91e262005-05-30 23:55:42 +0000168
169/*
170 * boot options & environment
171 */
172#define CONFIG_BOOTDELAY 3
173#define CONFIG_BOOTCOMMAND "run flash_self"
174#undef CONFIG_BOOTARGS
175#define CONFIG_EXTRA_ENV_SETTINGS \
176"clean_nv=erase fff20000 ffffffff\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100177"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
178"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
179"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
180"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
181"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
182"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
183"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
184"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
185"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
186"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
187"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
188"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
wdenkba91e262005-05-30 23:55:42 +0000189"fstype=cramfs\0" \
190"rootpath=/root_fs\0" \
191"uboot=PPC/u-boot.bin\0" \
192"kernel=PPC/uImage\0" \
193"kernel_addr=ffe00000\0" \
194"fs=PPC/root_fs\0" \
195"console=ttyS0\0" \
196"netdev=eth0\0" \
197"rootdev=31:3\0" \
198"ethaddr=00:09:4f:01:02:03\0" \
199"ipaddr=10.0.0.201\0" \
200"netmask=255.255.255.0\0" \
201"serverip=10.0.0.136\0" \
202"gatewayip=10.0.0.10\0" \
203"hostname=bastard\0" \
204""
205
206
207/*
208 * miscellaneous configurable options
209 */
210
211/* undef to save memory */
212#define CFG_LONGHELP
213
214/* monitor command prompt */
215#define CFG_PROMPT "=> "
216
217/* console i/o buffer size */
Jon Loeligera5562902007-07-08 15:31:57 -0500218#if defined(CONFIG_CMD_KGDB)
wdenkba91e262005-05-30 23:55:42 +0000219#define CFG_CBSIZE 1024
220#else
221#define CFG_CBSIZE 256
222#endif
223
224/* print buffer size */
225#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
226
227/* max number of command args */
228#define CFG_MAXARGS 16
229
230/* boot argument buffer size */
231#define CFG_BARGSIZE CFG_CBSIZE
232
233/* memtest works on */
234#define CFG_MEMTEST_START 0x00100000
235/* 1 ... 15 MB in DRAM */
236#define CFG_MEMTEST_END 0x00f00000
237/* full featured memtest */
238#define CFG_ALT_MEMTEST
239
240/* default load address */
241#define CFG_LOAD_ADDR 0x00100000
242
243/* decrementer freq: 1 ms ticks */
244#define CFG_HZ 1000
245
246/* configure flash */
247#define CFG_FLASH_BASE 0xff800000
248#define CFG_MAX_FLASH_BANKS 1
249#define CFG_MAX_FLASH_SECT 64
250#define CFG_FLASH_SIZE 8
251#undef CFG_FLASH_16BIT
252#define CFG_FLASH_ERASE_TOUT 240000
253#define CFG_FLASH_WRITE_TOUT 500
254#define CFG_FLASH_LOCK_TOUT 500
255#define CFG_FLASH_UNLOCK_TOUT 10000
256#define CFG_FLASH_PROTECTION
257
258/* monitor in flash */
259#define CFG_MONITOR_OFFSET 0x00700000
260
261/* environment in flash */
262#define CFG_ENV_IS_IN_FLASH 1
263#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000)
264#define CFG_ENV_SIZE 0x00020000
265#define CFG_ENV_SECT_SIZE 0x00020000
266
267/*
268 * Initial memory map for linux
269 * For booting Linux, the board info and command line data
270 * have to be in the first 8 MB of memory, since this is
271 * the maximum mapped by the Linux kernel during initialization.
272 */
wdenka87589d2005-06-10 10:00:19 +0000273#define CFG_BOOTMAPSZ (8 << 20)
wdenkba91e262005-05-30 23:55:42 +0000274
275/* hard reset configuration words */
276#ifdef CONFIG_CLKIN_66MHz
277#define CFG_HRCW_MASTER 0x04643050
278#else
279#error NO HRCW FOR 100MHZ SPECIFIED !!!
280#endif
281#define CFG_HRCW_SLAVE1 0x00000000
282#define CFG_HRCW_SLAVE2 0x00000000
283#define CFG_HRCW_SLAVE3 0x00000000
284#define CFG_HRCW_SLAVE4 0x00000000
285#define CFG_HRCW_SLAVE5 0x00000000
286#define CFG_HRCW_SLAVE6 0x00000000
287#define CFG_HRCW_SLAVE7 0x00000000
288
289/* internal memory mapped register */
290#define CFG_IMMR 0xF0000000
291
292/* definitions for initial stack pointer and data area (in DPRAM) */
293#define CFG_INIT_RAM_ADDR CFG_IMMR
294#define CFG_INIT_RAM_END 0x2000
295#define CFG_GBL_DATA_SIZE 128
296#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
297#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
298
299/*
300 * Start addresses for the final memory configuration
301 * (Set up by the startup code)
302 * Please note that CFG_SDRAM_BASE _must_ start at 0
303 */
304#define CFG_SDRAM_BASE 0x00000000
305#define CFG_SDRAM_SIZE (32*1024*1024)
306#define CFG_MONITOR_BASE TEXT_BASE
307#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
308#define CFG_MONITOR_LEN 0x00020000
309#define CFG_MALLOC_LEN 0x00020000
310
311/* boot flags */
312#define BOOTFLAG_COLD 0x01 /* normal power-on */
313#define BOOTFLAG_WARM 0x02 /* software reboot */
314
315/* cache configuration */
316#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */
Jon Loeligera5562902007-07-08 15:31:57 -0500317#if defined(CONFIG_CMD_KGDB)
wdenkba91e262005-05-30 23:55:42 +0000318#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */
319#endif
320
321/*
322 * HIDx - Hardware Implementation-dependent Registers
323 *-----------------------------------------------------------------------
324 * HID0 also contains cache control - initially enable both caches and
325 * invalidate contents, then the final state leaves only the instruction
326 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
327 * but Soft reset does not.
328 *
329 * HID1 has only read-only information - nothing to set.
330 */
331#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\
332 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
333#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
334#define CFG_HID2 0
335
336/* RMR - reset mode register - turn on checkstop reset enable */
337#define CFG_RMR RMR_CSRE
338
339/* BCR - bus configuration */
340#define CFG_BCR 0x00000000
341
342/* SIUMCR - siu module configuration */
343#define CFG_SIUMCR 0x4905c000
344
345/* SYPCR - system protection control */
346#if defined(CONFIG_WATCHDOG)
347#define CFG_SYPCR 0xffffff87
348#else
349#define CFG_SYPCR 0xffffff83
350#endif
351
352/* TMCNTSC - time counter status and control */
353/* clear interrupts XXX jse */
wdenka87589d2005-06-10 10:00:19 +0000354/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
wdenkba91e262005-05-30 23:55:42 +0000355#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
356 TMCNTSC_TCF|TMCNTSC_TCE)
357
358/* PISCR - periodic interrupt status and control */
359/* clear interrupts XXX jse */
wdenka87589d2005-06-10 10:00:19 +0000360/*#define CFG_PISCR (PISCR_PS) */
wdenkba91e262005-05-30 23:55:42 +0000361#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
362
363/* SCCR - system clock control */
364#define CFG_SCCR 0x000001a9
365
366/* RCCR - risc controller configuration */
367#define CFG_RCCR 0
368
369/*
370 * MEMORY MAP
371 * ----------
372 * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
373 * CS1 - SDRAM 32MB/64Bit base=0x00000000
374 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
375 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
376 * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
377 * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
378 * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
379 * x - IMMR 384KB base=0xf0000000
380 */
381/* XXX jse 100MHz TODO */
382#define CFG_BR0_PRELIM 0xff800801
383#define CFG_OR0_PRELIM 0xff801e44
384#define CFG_BR1_PRELIM 0x00000041
385#define CFG_OR1_PRELIM 0xfe002ec0
386#if 1
387#define CFG_BR2_PRELIM 0xf0101001
388#define CFG_OR2_PRELIM 0xfff00ef4
389#define CFG_BR3_PRELIM 0xf0201001
390#define CFG_OR3_PRELIM 0xfff00ef4
391#define CFG_BR4_PRELIM 0xf0301001
392#define CFG_OR4_PRELIM 0xfff00ef4
393#define CFG_BR5_PRELIM 0xf0401001
394#define CFG_OR5_PRELIM 0xfff00ef4
395#else
396#define CFG_BR2_PRELIM 0xf0101081
397#define CFG_OR2_PRELIM 0xfff00104
398#define CFG_BR3_PRELIM 0xf0201081
399#define CFG_OR3_PRELIM 0xfff00104
400#define CFG_BR4_PRELIM 0xf0301081
401#define CFG_OR4_PRELIM 0xfff00104
402#define CFG_BR5_PRELIM 0xf0401081
403#define CFG_OR5_PRELIM 0xfff00104
404#endif
405#define CFG_BR7_PRELIM 0xf0500881
406#define CFG_OR7_PRELIM 0xffff8104
407#define CFG_MPTPR 0x2700
408#define CFG_PSDMR 0x822a2452 /* optimal */
wdenka87589d2005-06-10 10:00:19 +0000409/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */
wdenkba91e262005-05-30 23:55:42 +0000410#define CFG_PSRT 0x1a
411
412/* "bad" address */
413#define CFG_RESET_ADDRESS 0x40000000
414
415#endif /* __CONFIG_H */