blob: 28ed9c03b944698f46477408de431271da1d2a4e [file] [log] [blame]
Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liu19580e62007-09-18 12:37:57 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Kim Phillipsfdfaa292015-03-17 12:00:45 -050011#define CONFIG_DISPLAY_BOARDINFO
12
Dave Liu19580e62007-09-18 12:37:57 +080013/*
14 * High Level Configuration Options
15 */
16#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050017#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080018#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
19
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
Dave Liu19580e62007-09-18 12:37:57 +080022/*
23 * System Clock Setup
24 */
25#ifdef CONFIG_PCISLAVE
26#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
27#else
28#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29#endif
30
31#ifndef CONFIG_SYS_CLK_FREQ
32#define CONFIG_SYS_CLK_FREQ 66000000
33#endif
34
35/*
36 * Hardware Reset Configuration Word
37 * if CLKIN is 66MHz, then
38 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
39 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080041 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
42 HRCWL_DDR_TO_SCB_CLK_1X1 |\
43 HRCWL_SVCOD_DIV_2 |\
44 HRCWL_CSB_TO_CLKIN_6X1 |\
45 HRCWL_CORE_TO_CSB_1_5X1)
46
47#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080049 HRCWH_PCI_AGENT |\
50 HRCWH_PCI1_ARBITER_DISABLE |\
51 HRCWH_CORE_ENABLE |\
52 HRCWH_FROM_0XFFF00100 |\
53 HRCWH_BOOTSEQ_DISABLE |\
54 HRCWH_SW_WATCHDOG_DISABLE |\
55 HRCWH_ROM_LOC_LOCAL_16BIT |\
56 HRCWH_RL_EXT_LEGACY |\
57 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
59 HRCWH_BIG_ENDIAN |\
60 HRCWH_LDP_CLEAR)
61#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080063 HRCWH_PCI_HOST |\
64 HRCWH_PCI1_ARBITER_ENABLE |\
65 HRCWH_CORE_ENABLE |\
66 HRCWH_FROM_0X00000100 |\
67 HRCWH_BOOTSEQ_DISABLE |\
68 HRCWH_SW_WATCHDOG_DISABLE |\
69 HRCWH_ROM_LOC_LOCAL_16BIT |\
70 HRCWH_RL_EXT_LEGACY |\
71 HRCWH_TSEC1M_IN_RGMII |\
72 HRCWH_TSEC2M_IN_RGMII |\
73 HRCWH_BIG_ENDIAN |\
74 HRCWH_LDP_CLEAR)
75#endif
76
Dave Liubd4458c2008-03-04 16:59:22 +080077/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger8d858082011-10-11 23:57:18 -050079#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080080
81/* System Priority Control Register */
Joe Hershberger8d858082011-10-11 23:57:18 -050082#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080083
Dave Liu19580e62007-09-18 12:37:57 +080084/*
Dave Liubd4458c2008-03-04 16:59:22 +080085 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080086 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
88#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
Joe Hershberger8d858082011-10-11 23:57:18 -050089#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +080090
91/*
92 * System IO Config
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_SICRH 0x00000000
95#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +080096
97/*
98 * Output Buffer Impedance
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +0800101
102#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
103#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400104#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800105
106/*
107 * IMMR new address
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800110
111/*
112 * DDR Setup
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
116#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
117#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
118#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2fef4022011-10-11 23:57:29 -0500119#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
120 | DDRCDR_ODT \
121 | DDRCDR_Q_DRN)
122 /* 0x80080001 */ /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800123
124#undef CONFIG_DDR_ECC /* support DDR ECC function */
125#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
126
127#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
128#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
129
130#if defined(CONFIG_SPD_EEPROM)
131#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
132#else
133/*
134 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800135 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800136 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_SIZE 512 /* MB */
139#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
Joe Hershberger8d858082011-10-11 23:57:18 -0500140#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500141 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
142 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
143 | CSCONFIG_ROW_BIT_14 \
144 | CSCONFIG_COL_BIT_10)
145 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500147#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
148 | (0 << TIMING_CFG0_WRT_SHIFT) \
149 | (0 << TIMING_CFG0_RRT_SHIFT) \
150 | (0 << TIMING_CFG0_WWT_SHIFT) \
151 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800155 /* 0x00620802 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500156#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
157 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
158 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
160 | (13 << TIMING_CFG1_REFREC_SHIFT) \
161 | (3 << TIMING_CFG1_WRREC_SHIFT) \
162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
163 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800164 /* 0x3935d322 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500165#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
166 | (6 << TIMING_CFG2_CPO_SHIFT) \
167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
168 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
171 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800172 /* 0x131088c8 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500173#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800175 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
177#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Joe Hershberger8d858082011-10-11 23:57:18 -0500178#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
179 | (0x1432 << SDRAM_MODE_SD_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800180 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500181#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800182#endif
183
184/*
185 * Memory test
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
188#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
189#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800190
191/*
192 * The reserved memory
193 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
197#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800198#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800200#endif
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger8d858082011-10-11 23:57:18 -0500203#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
204#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800205
206/*
207 * Initial RAM Base Address Setup
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200211#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500212#define CONFIG_SYS_GBL_DATA_OFFSET \
213 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800214
215/*
216 * Local Bus Configuration & Clock Setup
217 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500218#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
219#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500221#define CONFIG_FSL_ELBC 1
Dave Liu19580e62007-09-18 12:37:57 +0800222
223/*
224 * FLASH on the Local Bus
225 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500226#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200227#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger8d858082011-10-11 23:57:18 -0500228#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
229#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
230#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800231
Joe Hershberger8d858082011-10-11 23:57:18 -0500232 /* Window base at flash base */
233#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500234#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu19580e62007-09-18 12:37:57 +0800235
Joe Hershberger8d858082011-10-11 23:57:18 -0500236#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500237 | BR_PS_16 /* 16 bit port */ \
238 | BR_MS_GPCM /* MSEL = GPCM */ \
239 | BR_V) /* valid */
240#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Dave Liuded08312008-01-10 23:08:26 +0800241 | OR_UPM_XAM \
242 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400243 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800244 | OR_GPCM_XACS \
245 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500246 | OR_GPCM_TRLX_SET \
247 | OR_GPCM_EHTR_SET \
Joe Hershberger8d858082011-10-11 23:57:18 -0500248 | OR_GPCM_EAD)
Dave Liuded08312008-01-10 23:08:26 +0800249 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
252#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#undef CONFIG_SYS_FLASH_CHECKSUM
255#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
256#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800257
258/*
259 * BCSR on the Local Bus
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_BCSR 0xF8000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500262 /* Access window base at BCSR base */
263#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800265
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500266#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
267 | BR_PS_8 \
268 | BR_MS_GPCM \
269 | BR_V)
270 /* 0xF8000801 */
271#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
272 | OR_GPCM_XAM \
273 | OR_GPCM_CSNT \
274 | OR_GPCM_XACS \
275 | OR_GPCM_SCY_15 \
276 | OR_GPCM_TRLX_SET \
277 | OR_GPCM_EHTR_SET \
278 | OR_GPCM_EAD)
279 /* 0xFFFFE9F7 */
Dave Liu19580e62007-09-18 12:37:57 +0800280
281/*
282 * NAND Flash on the Local Bus
283 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400284#define CONFIG_CMD_NAND 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400285#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500286#define CONFIG_NAND_FSL_ELBC 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400287
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500288#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger8d858082011-10-11 23:57:18 -0500289#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500290 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger8d858082011-10-11 23:57:18 -0500291 | BR_PS_8 /* 8 bit port */ \
Dave Liu19580e62007-09-18 12:37:57 +0800292 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500293 | BR_V) /* valid */
294#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400295 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800296 | OR_FCM_CST \
297 | OR_FCM_CHT \
298 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400299 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800300 | OR_FCM_TRLX \
Joe Hershberger8d858082011-10-11 23:57:18 -0500301 | OR_FCM_EHTR)
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400302 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500305#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800306
307/*
308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_NS16550_SERIAL
312#define CONFIG_SYS_NS16550_REG_SIZE 1
313#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger8d858082011-10-11 23:57:18 -0500316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu19580e62007-09-18 12:37:57 +0800317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
319#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800320
Dave Liu19580e62007-09-18 12:37:57 +0800321/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200322#define CONFIG_SYS_I2C
323#define CONFIG_SYS_I2C_FSL
324#define CONFIG_SYS_FSL_I2C_SPEED 400000
325#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
326#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
327#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu19580e62007-09-18 12:37:57 +0800328
329/*
330 * Config on-board RTC
331 */
332#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800334
335/*
336 * General PCI
337 * Addresses are mapped 1-1.
338 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500339#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
340#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
341#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
343#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
344#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
345#define CONFIG_SYS_PCI_IO_BASE 0x00000000
346#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
347#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
350#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
351#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800352
Anton Vorontsov8b345572009-01-08 04:26:19 +0300353#define CONFIG_SYS_PCIE1_BASE 0xA0000000
354#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
355#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
356#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
357#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
358#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
359#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
360#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
361#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
362
363#define CONFIG_SYS_PCIE2_BASE 0xC0000000
364#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
365#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
366#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
367#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
368#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
369#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
370#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
371#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
372
Dave Liu19580e62007-09-18 12:37:57 +0800373#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000374#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400375#ifndef __ASSEMBLY__
376extern int board_pci_host_broken(void);
377#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500378#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800379#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
380
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400381#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530382#define CONFIG_USB_STORAGE
383#define CONFIG_USB_EHCI
384#define CONFIG_USB_EHCI_FSL
385#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400386
Dave Liu19580e62007-09-18 12:37:57 +0800387#define CONFIG_PCI_PNP /* do pci plug-and-play */
388
389#undef CONFIG_EEPRO100
390#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800392#endif /* CONFIG_PCI */
393
Dave Liu19580e62007-09-18 12:37:57 +0800394/*
395 * TSEC
396 */
397#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger8d858082011-10-11 23:57:18 -0500399#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger8d858082011-10-11 23:57:18 -0500401#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800402
403/*
404 * TSEC ethernet configuration
405 */
406#define CONFIG_MII 1 /* MII PHY management */
407#define CONFIG_TSEC1 1
408#define CONFIG_TSEC1_NAME "eTSEC0"
409#define CONFIG_TSEC2 1
410#define CONFIG_TSEC2_NAME "eTSEC1"
411#define TSEC1_PHY_ADDR 2
412#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400413#define TSEC1_PHY_ADDR_SGMII 8
414#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800415#define TSEC1_PHYIDX 0
416#define TSEC2_PHYIDX 0
417#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
418#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
419
420/* Options are: TSEC[0-1] */
421#define CONFIG_ETHPRIME "eTSEC1"
422
Dave Liu6f8c85e2008-03-26 22:56:36 +0800423/* SERDES */
424#define CONFIG_FSL_SERDES
425#define CONFIG_FSL_SERDES1 0xe3000
426#define CONFIG_FSL_SERDES2 0xe3100
427
Dave Liu19580e62007-09-18 12:37:57 +0800428/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800429 * SATA
430 */
431#define CONFIG_LIBATA
432#define CONFIG_FSL_SATA
433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800435#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger8d858082011-10-11 23:57:18 -0500437#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
438#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800439#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger8d858082011-10-11 23:57:18 -0500441#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
442#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800443
444#ifdef CONFIG_FSL_SATA
445#define CONFIG_LBA48
446#define CONFIG_CMD_SATA
447#define CONFIG_DOS_PARTITION
Dave Liu2eeb3e42008-03-26 22:57:19 +0800448#endif
449
450/*
Dave Liu19580e62007-09-18 12:37:57 +0800451 * Environment
452 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200454 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500455 #define CONFIG_ENV_ADDR \
456 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200457 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
458 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800459#else
Joe Hershberger8d858082011-10-11 23:57:18 -0500460 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200461 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200463 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800464#endif
465
466#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800468
469/*
470 * BOOTP options
471 */
472#define CONFIG_BOOTP_BOOTFILESIZE
473#define CONFIG_BOOTP_BOOTPATH
474#define CONFIG_BOOTP_GATEWAY
475#define CONFIG_BOOTP_HOSTNAME
476
Dave Liu19580e62007-09-18 12:37:57 +0800477/*
478 * Command line configuration.
479 */
Dave Liu19580e62007-09-18 12:37:57 +0800480#define CONFIG_CMD_DATE
481
482#if defined(CONFIG_PCI)
483 #define CONFIG_CMD_PCI
484#endif
485
Dave Liu19580e62007-09-18 12:37:57 +0800486#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500487#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu19580e62007-09-18 12:37:57 +0800488
489#undef CONFIG_WATCHDOG /* watchdog disabled */
490
Andy Fleminge1ac3872008-10-30 16:50:14 -0500491#define CONFIG_MMC 1
492
493#ifdef CONFIG_MMC
494#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800495#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleminge1ac3872008-10-30 16:50:14 -0500496#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Andy Fleminge1ac3872008-10-30 16:50:14 -0500497#define CONFIG_GENERIC_MMC
Andy Fleminge1ac3872008-10-30 16:50:14 -0500498#define CONFIG_DOS_PARTITION
499#endif
500
Dave Liu19580e62007-09-18 12:37:57 +0800501/*
502 * Miscellaneous configurable options
503 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_LONGHELP /* undef to save memory */
505#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu19580e62007-09-18 12:37:57 +0800506
507#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800509#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800511#endif
512
Joe Hershberger8d858082011-10-11 23:57:18 -0500513 /* Print Buffer Size */
514#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
515#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
516 /* Boot Argument Buffer Size */
517#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu19580e62007-09-18 12:37:57 +0800518
519/*
520 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700521 * have to be in the first 256 MB of memory, since this is
Dave Liu19580e62007-09-18 12:37:57 +0800522 * the maximum mapped by the Linux kernel during initialization.
523 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500524#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu19580e62007-09-18 12:37:57 +0800525
526/*
527 * Core HID Setup
528 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500529#define CONFIG_SYS_HID0_INIT 0x000000000
530#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
531 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800533
534/*
Dave Liu19580e62007-09-18 12:37:57 +0800535 * MMU Setup
536 */
Becky Bruce31d82672008-05-08 19:02:12 -0500537#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800538
539/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
541#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800542
Joe Hershberger8d858082011-10-11 23:57:18 -0500543#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500544 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500545 | BATL_MEMCOHERENCE)
546#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
547 | BATU_BL_256M \
548 | BATU_VS \
549 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
551#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800552
Joe Hershberger8d858082011-10-11 23:57:18 -0500553#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500554 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500555 | BATL_MEMCOHERENCE)
556#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
557 | BATU_BL_256M \
558 | BATU_VS \
559 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
561#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800562
563/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500564#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500565 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500566 | BATL_CACHEINHIBIT \
567 | BATL_GUARDEDSTORAGE)
568#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
569 | BATU_BL_8M \
570 | BATU_VS \
571 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
573#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800574
575/* BCSR: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500576#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500577 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500578 | BATL_CACHEINHIBIT \
579 | BATL_GUARDEDSTORAGE)
580#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
581 | BATU_BL_128K \
582 | BATU_VS \
583 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
585#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800586
587/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500588#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500589 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500590 | BATL_MEMCOHERENCE)
591#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
592 | BATU_BL_32M \
593 | BATU_VS \
594 | BATU_VP)
595#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500596 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500597 | BATL_CACHEINHIBIT \
598 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800600
601/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500602#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger8d858082011-10-11 23:57:18 -0500603#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
604 | BATU_BL_128K \
605 | BATU_VS \
606 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
608#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800609
610#ifdef CONFIG_PCI
611/* PCI MEM space: cacheable */
Joe Hershberger8d858082011-10-11 23:57:18 -0500612#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500613 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500614 | BATL_MEMCOHERENCE)
615#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
616 | BATU_BL_256M \
617 | BATU_VS \
618 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
620#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800621/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500622#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500623 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500624 | BATL_CACHEINHIBIT \
625 | BATL_GUARDEDSTORAGE)
626#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
627 | BATU_BL_256M \
628 | BATU_VS \
629 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200630#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
631#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800632#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#define CONFIG_SYS_IBAT6L (0)
634#define CONFIG_SYS_IBAT6U (0)
635#define CONFIG_SYS_IBAT7L (0)
636#define CONFIG_SYS_IBAT7U (0)
637#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
638#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
639#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
640#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800641#endif
642
Dave Liu19580e62007-09-18 12:37:57 +0800643#if defined(CONFIG_CMD_KGDB)
644#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu19580e62007-09-18 12:37:57 +0800645#endif
646
647/*
648 * Environment Configuration
649 */
650
651#define CONFIG_ENV_OVERWRITE
652
653#if defined(CONFIG_TSEC_ENET)
654#define CONFIG_HAS_ETH0
Dave Liu19580e62007-09-18 12:37:57 +0800655#define CONFIG_HAS_ETH1
Dave Liu19580e62007-09-18 12:37:57 +0800656#endif
657
658#define CONFIG_BAUDRATE 115200
659
Kim Phillips79f516b2009-08-21 16:34:38 -0500660#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800661
662#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
663#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
664
665#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger8d858082011-10-11 23:57:18 -0500666 "netdev=eth0\0" \
667 "consoledev=ttyS0\0" \
668 "ramdiskaddr=1000000\0" \
669 "ramdiskfile=ramfs.83xx\0" \
670 "fdtaddr=780000\0" \
671 "fdtfile=mpc8379_mds.dtb\0" \
672 ""
Dave Liu19580e62007-09-18 12:37:57 +0800673
674#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500675 "setenv bootargs root=/dev/nfs rw " \
676 "nfsroot=$serverip:$rootpath " \
677 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
678 "$netdev:off " \
679 "console=$consoledev,$baudrate $othbootargs;" \
680 "tftp $loadaddr $bootfile;" \
681 "tftp $fdtaddr $fdtfile;" \
682 "bootm $loadaddr - $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800683
684#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500685 "setenv bootargs root=/dev/ram rw " \
686 "console=$consoledev,$baudrate $othbootargs;" \
687 "tftp $ramdiskaddr $ramdiskfile;" \
688 "tftp $loadaddr $bootfile;" \
689 "tftp $fdtaddr $fdtfile;" \
690 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800691
Dave Liu19580e62007-09-18 12:37:57 +0800692#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
693
694#endif /* __CONFIG_H */