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Mike Frysingere5483212008-10-12 21:45:05 -04001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for CM-BF561 board
Mike Frysingere5483212008-10-12 21:45:05 -04003 */
4
5#ifndef __CONFIG_CM_BF561_H__
6#define __CONFIG_CM_BF561_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingere5483212008-10-12 21:45:05 -04009
Mike Frysingere5483212008-10-12 21:45:05 -040010/*
11 * Processor Settings
12 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050013#define CONFIG_BFIN_CPU bf561-0.3
Mike Frysingere5483212008-10-12 21:45:05 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
15
Mike Frysingere5483212008-10-12 21:45:05 -040016/*
17 * Clock Settings
18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
20 */
21/* CONFIG_CLKIN_HZ is any value in Hz */
22#define CONFIG_CLKIN_HZ 25000000
23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
24/* 1 = CLKIN / 2 */
25#define CONFIG_CLKIN_HALF 0
26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
27/* 1 = bypass PLL */
28#define CONFIG_PLL_BYPASS 0
29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
30/* Values can range from 0-63 (where 0 means 64) */
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040031#define CONFIG_VCO_MULT 20
Mike Frysingere5483212008-10-12 21:45:05 -040032/* CCLK_DIV controls the core clock divider */
33/* Values can be 1, 2, 4, or 8 ONLY */
34#define CONFIG_CCLK_DIV 1
35/* SCLK_DIV controls the system clock divider */
36/* Values can range from 1-15 */
37#define CONFIG_SCLK_DIV 5
38
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040039/* Decrease core voltage */
40#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
41
Mike Frysingere5483212008-10-12 21:45:05 -040042/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 9
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
49#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
50
51#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
Mike Frysingere5483212008-10-12 21:45:05 -040058/*
59 * Network Settings
60 */
61#define ADI_CMDS_NETWORK 1
Harald Krapfenbauer6a0be8f2010-01-22 17:15:55 -050062#define CONFIG_SMC911X 1
63#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
64#define CONFIG_SMC911X_16_BIT
Mike Frysingere5483212008-10-12 21:45:05 -040065#define CONFIG_HOSTNAME cm-bf561
Mike Frysingere5483212008-10-12 21:45:05 -040066
Mike Frysingere5483212008-10-12 21:45:05 -040067/*
68 * Flash Settings
69 */
70#define CONFIG_FLASH_CFI_DRIVER
71#define CONFIG_SYS_FLASH_BASE 0x20000000
72#define CONFIG_SYS_FLASH_CFI
73#define CONFIG_SYS_FLASH_PROTECTION
74#define CONFIG_SYS_MAX_FLASH_BANKS 1
75#define CONFIG_SYS_MAX_FLASH_SECT 67
76
Mike Frysingere5483212008-10-12 21:45:05 -040077/*
78 * Env Storage Settings
79 */
80#define CONFIG_ENV_IS_IN_FLASH 1
81#define CONFIG_ENV_OFFSET 0x20000
82#define CONFIG_ENV_SECT_SIZE 0x20000
83#define CONFIG_ENV_SIZE 0x10000
Harald Krapfenbauer6a0be8f2010-01-22 17:15:55 -050084#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingere5483212008-10-12 21:45:05 -040085
Mike Frysingere5483212008-10-12 21:45:05 -040086/*
87 * Misc Settings
88 */
89#define CONFIG_BAUDRATE 115200
90#define CONFIG_UART_CONSOLE 0
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040091#define CONFIG_BOOTCOMMAND "run flashboot"
92#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
Mike Frysingere5483212008-10-12 21:45:05 -040093
94/*
95 * Pull in common ADI header for remaining command/environment setup
96 */
97#include <configs/bfin_adi_common.h>
98
Mike Frysingere5483212008-10-12 21:45:05 -040099#endif