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Dinh Nguyen77754402012-10-04 06:46:02 +00001/*
Pavel Machek5095ee02014-09-08 14:08:45 +02002 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Dinh Nguyen77754402012-10-04 06:46:02 +00003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen77754402012-10-04 06:46:02 +00005 */
Pavel Machek5095ee02014-09-08 14:08:45 +02006#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
7#define __CONFIG_SOCFPGA_CYCLONE5_H__
Dinh Nguyen77754402012-10-04 06:46:02 +00008
Dinh Nguyen871c24b2015-11-23 17:27:17 -06009#include <asm/arch/base_addr_ac5.h>
Dinh Nguyen77754402012-10-04 06:46:02 +000010
Marek Vasut47f9b4e2014-09-08 14:08:45 +020011/* U-Boot Commands */
12#define CONFIG_SYS_NO_FLASH
Marek Vasut47f9b4e2014-09-08 14:08:45 +020013#define CONFIG_DOS_PARTITION
14#define CONFIG_FAT_WRITE
15#define CONFIG_HW_WATCHDOG
16
Pavel Machek5095ee02014-09-08 14:08:45 +020017/* Memory configurations */
Marek Vasut47f9b4e2014-09-08 14:08:45 +020018#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
Dinh Nguyen77754402012-10-04 06:46:02 +000019
Marek Vasut47f9b4e2014-09-08 14:08:45 +020020/* Booting Linux */
21#define CONFIG_BOOTDELAY 3
22#define CONFIG_BOOTFILE "zImage"
Anatolij Gustschin116f5d52014-11-07 01:12:03 +010023#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
Chin Liang See97ce2742014-09-19 05:33:19 -050024#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Marek Vasut47f9b4e2014-09-08 14:08:45 +020025#define CONFIG_BOOTCOMMAND "run ramboot"
Chin Liang See97ce2742014-09-19 05:33:19 -050026#else
Marek Vasut47f9b4e2014-09-08 14:08:45 +020027#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
28#endif
Marek Vasut4c6d8b92015-07-22 06:18:19 +020029#define CONFIG_LOADADDR 0x01000000
Marek Vasut47f9b4e2014-09-08 14:08:45 +020030#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
31
Pavel Machek5095ee02014-09-08 14:08:45 +020032/* Ethernet on SoC (EMAC) */
33#if defined(CONFIG_CMD_NET)
Marek Vasut47f9b4e2014-09-08 14:08:45 +020034#define CONFIG_PHY_MICREL
35#define CONFIG_PHY_MICREL_KSZ9021
Chin Liang See97ce2742014-09-19 05:33:19 -050036#endif
Dinh Nguyen77754402012-10-04 06:46:02 +000037
Dinh Nguyen68a3e322015-09-23 15:38:01 -050038#define CONFIG_ENV_IS_IN_MMC
Dinh Nguyen68a3e322015-09-23 15:38:01 -050039
Pavel Machek5095ee02014-09-08 14:08:45 +020040/* Extra Environment */
Dinh Nguyen77754402012-10-04 06:46:02 +000041#define CONFIG_EXTRA_ENV_SETTINGS \
42 "verify=n\0" \
Marek Vasutf6060ce2016-04-03 19:11:12 +020043 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +000044 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
45 "bootm ${loadaddr} - ${fdt_addr}\0" \
Chin Liang See97ce2742014-09-19 05:33:19 -050046 "bootimage=zImage\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +000047 "fdt_addr=100\0" \
Chin Liang See97ce2742014-09-19 05:33:19 -050048 "fdtimage=socfpga.dtb\0" \
Chin Liang See97ce2742014-09-19 05:33:19 -050049 "bootm ${loadaddr} - ${fdt_addr}\0" \
50 "mmcroot=/dev/mmcblk0p2\0" \
51 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
52 " root=${mmcroot} rw rootwait;" \
53 "bootz ${loadaddr} - ${fdt_addr}\0" \
54 "mmcload=mmc rescan;" \
Marek Vasut2f210632014-09-19 13:28:47 +020055 "load mmc 0:1 ${loadaddr} ${bootimage};" \
56 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
Chin Liang Seed9f2bd42015-12-22 15:32:35 +080057 "qspiload=sf probe && mtdparts default && run ubiload\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +000058 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
Chin Liang See0f28b1a2015-12-22 15:32:39 +080059 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
60 "bootz ${loadaddr} - ${fdt_addr}\0" \
Chin Liang Seedc932802015-12-22 15:32:31 +080061 "ubiload=ubi part UBI && ubifsmount ubi0 && " \
62 "ubifsload ${loadaddr} /boot/${bootimage} && " \
63 "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
Dinh Nguyen77754402012-10-04 06:46:02 +000064
Pavel Machek5095ee02014-09-08 14:08:45 +020065/* The rest of the configuration is shared */
66#include <configs/socfpga_common.h>
Dinh Nguyen77754402012-10-04 06:46:02 +000067
Pavel Machek5095ee02014-09-08 14:08:45 +020068#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */