| Horatiu Vultur | d118205 | 2019-01-12 18:56:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2018 Microsemi Corporation |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <1>; |
| 9 | compatible = "mscc,jr2"; |
| 10 | |
| 11 | cpus { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <0>; |
| 14 | |
| 15 | cpu@0 { |
| 16 | compatible = "mips,mips24KEc"; |
| 17 | device_type = "cpu"; |
| 18 | clocks = <&cpu_clk>; |
| 19 | reg = <0>; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &uart0; |
| 25 | }; |
| 26 | |
| 27 | cpuintc: interrupt-controller@0 { |
| 28 | #address-cells = <0>; |
| 29 | #interrupt-cells = <1>; |
| 30 | interrupt-controller; |
| 31 | compatible = "mti,cpu-interrupt-controller"; |
| 32 | }; |
| 33 | |
| 34 | cpu_clk: cpu-clock { |
| 35 | compatible = "fixed-clock"; |
| 36 | #clock-cells = <0>; |
| 37 | clock-frequency = <500000000>; |
| 38 | }; |
| 39 | |
| 40 | ahb_clk: ahb-clk { |
| 41 | compatible = "fixed-clock"; |
| 42 | #clock-cells = <0>; |
| 43 | clock-frequency = <250000000>; |
| 44 | }; |
| 45 | |
| 46 | ahb { |
| 47 | compatible = "simple-bus"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | ranges = <0 0x70000000 0x2000000>; |
| 51 | |
| 52 | interrupt-parent = <&intc>; |
| 53 | |
| 54 | cpu_ctrl: syscon@0 { |
| 55 | compatible = "mscc,jr2-cpu-syscon", "syscon"; |
| 56 | reg = <0x0 0x2c>; |
| 57 | }; |
| 58 | |
| 59 | intc: interrupt-controller@70 { |
| 60 | compatible = "mscc,jr2-icpu-intr"; |
| 61 | reg = <0x70 0x94>; |
| 62 | #interrupt-cells = <1>; |
| 63 | interrupt-controller; |
| 64 | interrupt-parent = <&cpuintc>; |
| 65 | interrupts = <2>; |
| 66 | }; |
| 67 | |
| 68 | uart0: serial@100000 { |
| 69 | pinctrl-0 = <&uart_pins>; |
| 70 | pinctrl-names = "default"; |
| 71 | compatible = "ns16550a"; |
| 72 | reg = <0x100000 0x20>; |
| 73 | interrupts = <6>; |
| 74 | clocks = <&ahb_clk>; |
| 75 | reg-io-width = <4>; |
| 76 | reg-shift = <2>; |
| 77 | |
| 78 | status = "disabled"; |
| 79 | }; |
| 80 | |
| 81 | uart2: serial@100800 { |
| 82 | pinctrl-0 = <&uart2_pins>; |
| 83 | pinctrl-names = "default"; |
| 84 | compatible = "ns16550a"; |
| 85 | reg = <0x100800 0x20>; |
| 86 | interrupts = <7>; |
| 87 | clocks = <&ahb_clk>; |
| 88 | reg-io-width = <4>; |
| 89 | reg-shift = <2>; |
| 90 | |
| 91 | status = "disabled"; |
| 92 | }; |
| 93 | |
| 94 | spi0: spi-master@101000 { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | compatible = "snps,dw-apb-ssi"; |
| 98 | reg = <0x101000 0x40>; |
| 99 | num-chipselect = <4>; |
| 100 | bus-num = <0>; |
| 101 | reg-io-width = <4>; |
| 102 | reg-shift = <2>; |
| 103 | spi-max-frequency = <18000000>; /* input clock */ |
| 104 | clocks = <&ahb_clk>; |
| 105 | |
| 106 | status = "disabled"; |
| 107 | }; |
| 108 | |
| 109 | reset@1010008 { |
| 110 | compatible = "mscc,jr2-chip-reset"; |
| 111 | reg = <0x1010008 0x4>; |
| 112 | }; |
| 113 | |
| 114 | gpio: pinctrl@1070034 { |
| 115 | compatible = "mscc,jaguar2-pinctrl"; |
| 116 | reg = <0x1010038 0x90>; |
| 117 | gpio-controller; |
| 118 | #gpio-cells = <2>; |
| 119 | gpio-ranges = <&gpio 0 0 64>; |
| 120 | |
| 121 | sgpio_pins: sgpio-pins { |
| 122 | pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; |
| 123 | function = "sg0"; |
| 124 | }; |
| 125 | |
| 126 | sgpio1_pins: sgpio1-pins { |
| 127 | pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; |
| 128 | function = "sg1"; |
| 129 | }; |
| 130 | |
| 131 | sgpio2_pins: sgpio2-pins { |
| 132 | pins = "GPIO_30", "GPIO_31", |
| 133 | "GPIO_32", "GPIO_33"; |
| 134 | function = "sg2"; |
| 135 | }; |
| 136 | |
| 137 | uart_pins: uart-pins { |
| 138 | pins = "GPIO_10", "GPIO_11"; |
| 139 | function = "uart"; |
| 140 | }; |
| 141 | |
| 142 | uart2_pins: uart2-pins { |
| 143 | pins = "GPIO_24", "GPIO_25"; |
| 144 | function = "uart2"; |
| 145 | }; |
| 146 | }; |
| 147 | |
| 148 | sgpio: gpio@1010150 { |
| 149 | compatible = "mscc,ocelot-sgpio"; |
| 150 | status = "disabled"; |
| 151 | pinctrl-0 = <&sgpio_pins>; |
| 152 | pinctrl-names = "default"; |
| 153 | reg = <0x1010150 0x100>; |
| 154 | gpio-controller; |
| 155 | #gpio-cells = <2>; |
| 156 | gpio-ranges = <&sgpio 0 0 64>; |
| 157 | gpio-bank-name = "sgpio0_"; |
| 158 | sgpio-clock = <0x14>; |
| 159 | }; |
| 160 | |
| 161 | sgpio1: gpio@101025c { |
| 162 | compatible = "mscc,ocelot-sgpio"; |
| 163 | status = "disabled"; |
| 164 | pinctrl-0 = <&sgpio1_pins>; |
| 165 | pinctrl-names = "default"; |
| 166 | reg = <0x101025c 0x100>; |
| 167 | gpio-controller; |
| 168 | #gpio-cells = <2>; |
| 169 | gpio-ranges = <&sgpio1 0 0 64>; |
| 170 | gpio-bank-name = "sgpio1_"; |
| 171 | sgpio-clock = <0x14>; |
| 172 | }; |
| 173 | |
| 174 | sgpio2: gpio@1010368 { |
| 175 | compatible = "mscc,ocelot-sgpio"; |
| 176 | status = "disabled"; |
| 177 | pinctrl-0 = <&sgpio2_pins>; |
| 178 | pinctrl-names = "default"; |
| 179 | reg = <0x1010368 0x100>; |
| 180 | gpio-controller; |
| 181 | #gpio-cells = <2>; |
| 182 | gpio-ranges = <&sgpio2 0 0 64>; |
| 183 | gpio-bank-name = "sgpio2_"; |
| 184 | sgpio-clock = <0x14>; |
| 185 | }; |
| Horatiu Vultur | 1141176 | 2019-04-03 19:54:47 +0200 | [diff] [blame] | 186 | |
| 187 | switch: switch@1010000 { |
| 188 | compatible = "mscc,vsc7454-switch"; |
| 189 | reg = <0x01040000 0x0100>, // VTSS_TO_DEV_0 |
| 190 | <0x01050000 0x0100>, // VTSS_TO_DEV_1 |
| 191 | <0x01060000 0x0100>, // VTSS_TO_DEV_2 |
| 192 | <0x01070000 0x0100>, // VTSS_TO_DEV_3 |
| 193 | <0x01080000 0x0100>, // VTSS_TO_DEV_4 |
| 194 | <0x01090000 0x0100>, // VTSS_TO_DEV_5 |
| 195 | <0x010a0000 0x0100>, // VTSS_TO_DEV_6 |
| 196 | <0x010b0000 0x0100>, // VTSS_TO_DEV_7 |
| 197 | <0x010c0000 0x0100>, // VTSS_TO_DEV_8 |
| 198 | <0x010d0000 0x0100>, // VTSS_TO_DEV_9 |
| 199 | <0x010e0000 0x0100>, // VTSS_TO_DEV_10 |
| 200 | <0x010f0000 0x0100>, // VTSS_TO_DEV_11 |
| 201 | <0x01100000 0x0100>, // VTSS_TO_DEV_12 |
| 202 | <0x01110000 0x0100>, // VTSS_TO_DEV_13 |
| 203 | <0x01120000 0x0100>, // VTSS_TO_DEV_14 |
| 204 | <0x01130000 0x0100>, // VTSS_TO_DEV_15 |
| 205 | <0x01140000 0x0100>, // VTSS_TO_DEV_16 |
| 206 | <0x01150000 0x0100>, // VTSS_TO_DEV_17 |
| 207 | <0x01160000 0x0100>, // VTSS_TO_DEV_18 |
| 208 | <0x01170000 0x0100>, // VTSS_TO_DEV_19 |
| 209 | <0x01180000 0x0100>, // VTSS_TO_DEV_20 |
| 210 | <0x01190000 0x0100>, // VTSS_TO_DEV_21 |
| 211 | <0x011a0000 0x0100>, // VTSS_TO_DEV_22 |
| 212 | <0x011b0000 0x0100>, // VTSS_TO_DEV_23 |
| 213 | <0x011c0000 0x0100>, // VTSS_TO_DEV_24 |
| 214 | <0x011d0000 0x0100>, // VTSS_TO_DEV_25 |
| 215 | <0x011e0000 0x0100>, // VTSS_TO_DEV_26 |
| 216 | <0x011f0000 0x0100>, // VTSS_TO_DEV_27 |
| 217 | <0x01200000 0x0100>, // VTSS_TO_DEV_28 |
| 218 | <0x01210000 0x0100>, // VTSS_TO_DEV_29 |
| 219 | <0x01220000 0x0100>, // VTSS_TO_DEV_30 |
| 220 | <0x01230000 0x0100>, // VTSS_TO_DEV_31 |
| 221 | <0x01240000 0x0100>, // VTSS_TO_DEV_32 |
| 222 | <0x01250000 0x0100>, // VTSS_TO_DEV_33 |
| 223 | <0x01260000 0x0100>, // VTSS_TO_DEV_34 |
| 224 | <0x01270000 0x0100>, // VTSS_TO_DEV_35 |
| 225 | <0x01280000 0x0100>, // VTSS_TO_DEV_36 |
| 226 | <0x01290000 0x0100>, // VTSS_TO_DEV_37 |
| 227 | <0x012a0000 0x0100>, // VTSS_TO_DEV_38 |
| 228 | <0x012b0000 0x0100>, // VTSS_TO_DEV_39 |
| 229 | <0x012c0000 0x0100>, // VTSS_TO_DEV_40 |
| 230 | <0x012d0000 0x0100>, // VTSS_TO_DEV_41 |
| 231 | <0x012e0000 0x0100>, // VTSS_TO_DEV_42 |
| 232 | <0x012f0000 0x0100>, // VTSS_TO_DEV_43 |
| 233 | <0x01300000 0x0100>, // VTSS_TO_DEV_44 |
| 234 | <0x01310000 0x0100>, // VTSS_TO_DEV_45 |
| 235 | <0x01320000 0x0100>, // VTSS_TO_DEV_46 |
| 236 | <0x01330000 0x0100>, // VTSS_TO_DEV_47 |
| 237 | <0x01f00000 0x100000>, // ANA_AC |
| 238 | <0x01d00000 0x100000>, // ANA_CL |
| 239 | <0x01e00000 0x100000>, // ANA_L2 |
| 240 | <0x01410000 0x10000>, // ASM |
| 241 | <0x01460000 0x10000>, // HSIO |
| 242 | <0x01420000 0x00000>, // LRN |
| 243 | <0x017d0000 0x10000>, // QFWD |
| 244 | <0x01020000 0x20000>, // QS |
| 245 | <0x017e0000 0x10000>, // QSYS |
| 246 | <0x01b00000 0x80000>; // REW |
| 247 | reg-names = "port0", "port1", "port2", "port3", "port4", |
| 248 | "port5", "port6", "port7", "port8", "port9", |
| 249 | "port10", "port11", "port12", "port13", |
| 250 | "port14", "port15", "port16", "port17", |
| 251 | "port18", "port19", "port20", "port21", |
| 252 | "port22", "port23", "port24", "port25", |
| 253 | "port26", "port27", "port28", "port29", |
| 254 | "port30", "port31", "port32", "port33", |
| 255 | "port34", "port35", "port36", "port37", |
| 256 | "port38", "port39", "port40", "port41", |
| 257 | "port42", "port43", "port44", "port45", |
| 258 | "port46", "port47", "ana_ac", "ana_cl", |
| 259 | "ana_l2", "asm", "hsio", "lrn", "qfwd", |
| 260 | "qs", "qsys", "rew"; |
| 261 | status = "okay"; |
| 262 | |
| 263 | ethernet-ports { |
| 264 | #address-cells = <1>; |
| 265 | #size-cells = <0>; |
| 266 | }; |
| 267 | }; |
| 268 | |
| 269 | mdio0: mdio@010100c8 { |
| 270 | #address-cells = <1>; |
| 271 | #size-cells = <0>; |
| 272 | compatible = "mscc,jr2-miim"; |
| 273 | reg = <0x010100c8 0x24>; |
| 274 | status = "disabled"; |
| 275 | }; |
| 276 | |
| 277 | mdio1: mdio@010100ec { |
| 278 | #address-cells = <1>; |
| 279 | #size-cells = <0>; |
| 280 | compatible = "mscc,jr2-miim"; |
| 281 | reg = <0x010100ec 0x24>; |
| 282 | status = "disabled"; |
| 283 | }; |
| 284 | |
| 285 | mdio2: mdio@01010110 { |
| 286 | #address-cells = <1>; |
| 287 | #size-cells = <0>; |
| 288 | compatible = "mscc,jr2-miim"; |
| 289 | reg = <0x01010110 0x24>; |
| 290 | status = "disabled"; |
| 291 | }; |
| 292 | |
| 293 | hsio: syscon@10d0000 { |
| 294 | compatible = "mscc,jr2-hsio", "syscon", "simple-mfd"; |
| 295 | reg = <0x10d0000 0x10000>; |
| 296 | |
| 297 | serdes_hsio: serdes_hsio { |
| 298 | compatible = "mscc,vsc7454-serdes"; |
| 299 | #phy-cells = <3>; |
| 300 | }; |
| 301 | }; |
| Horatiu Vultur | d118205 | 2019-01-12 18:56:57 +0100 | [diff] [blame] | 302 | }; |
| 303 | }; |