wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * ARM Ltd. |
| 7 | * Philippe Robin, <philippe.robin@arm.com> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
Andreas Engel | 48d0192 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 28 | /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 29 | |
| 30 | #include <common.h> |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 31 | #include <watchdog.h> |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 32 | #include <asm/io.h> |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 33 | #include <serial.h> |
| 34 | #include <linux/compiler.h> |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 35 | #include "serial_pl01x.h" |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 36 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 37 | /* |
| 38 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 |
| 39 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 |
| 40 | * Versatile PB has four UARTs. |
| 41 | */ |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 42 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
wdenk | 6705d81 | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 43 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
| 44 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 45 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 46 | static void pl01x_putc (int portnum, char c); |
| 47 | static int pl01x_getc (int portnum); |
| 48 | static int pl01x_tstc (int portnum); |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 49 | unsigned int baudrate = CONFIG_BAUDRATE; |
| 50 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 51 | |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 52 | static struct pl01x_regs *pl01x_get_regs(int portnum) |
| 53 | { |
| 54 | return (struct pl01x_regs *) port[portnum]; |
| 55 | } |
| 56 | |
Andreas Engel | 48d0192 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 57 | #ifdef CONFIG_PL010_SERIAL |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 58 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 59 | static int pl01x_serial_init(void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 60 | { |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 61 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 62 | unsigned int divisor; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 63 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 64 | /* First, disable everything */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 65 | writel(0, ®s->pl010_cr); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 66 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 67 | /* Set baud rate */ |
| 68 | switch (baudrate) { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 69 | case 9600: |
| 70 | divisor = UART_PL010_BAUD_9600; |
| 71 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 72 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 73 | case 19200: |
| 74 | divisor = UART_PL010_BAUD_9600; |
| 75 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 76 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 77 | case 38400: |
| 78 | divisor = UART_PL010_BAUD_38400; |
| 79 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 80 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 81 | case 57600: |
| 82 | divisor = UART_PL010_BAUD_57600; |
| 83 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 84 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 85 | case 115200: |
| 86 | divisor = UART_PL010_BAUD_115200; |
| 87 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 88 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 89 | default: |
| 90 | divisor = UART_PL010_BAUD_38400; |
| 91 | } |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 92 | |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 93 | writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); |
| 94 | writel(divisor & 0xff, ®s->pl010_lcrl); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 95 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 96 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 97 | writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 98 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 99 | /* Finally, enable the UART */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 100 | writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 101 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 102 | return 0; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 103 | } |
| 104 | |
Andreas Engel | 48d0192 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 105 | #endif /* CONFIG_PL010_SERIAL */ |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 106 | |
Andreas Engel | 48d0192 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 107 | #ifdef CONFIG_PL011_SERIAL |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 108 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 109 | static int pl01x_serial_init(void) |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 110 | { |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 111 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 112 | unsigned int temp; |
| 113 | unsigned int divider; |
| 114 | unsigned int remainder; |
| 115 | unsigned int fraction; |
John Rigby | 910f1ae | 2011-04-19 10:42:39 +0000 | [diff] [blame] | 116 | unsigned int lcr; |
| 117 | |
| 118 | #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT |
| 119 | /* Empty RX fifo if necessary */ |
| 120 | if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { |
| 121 | while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) |
| 122 | readl(®s->dr); |
| 123 | } |
| 124 | #endif |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 125 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 126 | /* First, disable everything */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 127 | writel(0, ®s->pl011_cr); |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 128 | |
| 129 | /* |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 130 | * Set baud rate |
| 131 | * |
| 132 | * IBRD = UART_CLK / (16 * BAUD_RATE) |
| 133 | * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 134 | */ |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 135 | temp = 16 * baudrate; |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 136 | divider = CONFIG_PL011_CLOCK / temp; |
| 137 | remainder = CONFIG_PL011_CLOCK % temp; |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 138 | temp = (8 * remainder) / baudrate; |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 139 | fraction = (temp >> 1) + (temp & 1); |
| 140 | |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 141 | writel(divider, ®s->pl011_ibrd); |
| 142 | writel(fraction, ®s->pl011_fbrd); |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 143 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 144 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
John Rigby | 910f1ae | 2011-04-19 10:42:39 +0000 | [diff] [blame] | 145 | lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; |
| 146 | writel(lcr, ®s->pl011_lcrh); |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 147 | |
John Rigby | 910f1ae | 2011-04-19 10:42:39 +0000 | [diff] [blame] | 148 | #ifdef CONFIG_PL011_SERIAL_RLCR |
| 149 | { |
| 150 | int i; |
| 151 | |
| 152 | /* |
| 153 | * Program receive line control register after waiting |
| 154 | * 10 bus cycles. Delay be writing to readonly register |
| 155 | * 10 times |
| 156 | */ |
| 157 | for (i = 0; i < 10; i++) |
| 158 | writel(lcr, ®s->fr); |
| 159 | |
| 160 | writel(lcr, ®s->pl011_rlcr); |
Mathieu J. Poirier | 84dee30 | 2012-08-03 11:05:12 +0000 | [diff] [blame] | 161 | /* lcrh needs to be set again for change to be effective */ |
| 162 | writel(lcr, ®s->pl011_lcrh); |
John Rigby | 910f1ae | 2011-04-19 10:42:39 +0000 | [diff] [blame] | 163 | } |
| 164 | #endif |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 165 | /* Finally, enable the UART */ |
Joshua Housh | 10501df | 2012-12-02 17:09:26 +0000 | [diff] [blame] | 166 | writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | |
| 167 | UART_PL011_CR_RTS, ®s->pl011_cr); |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 168 | |
| 169 | return 0; |
| 170 | } |
| 171 | |
Andreas Engel | 48d0192 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 172 | #endif /* CONFIG_PL011_SERIAL */ |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 173 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 174 | static void pl01x_serial_putc(const char c) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 175 | { |
| 176 | if (c == '\n') |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 177 | pl01x_putc (CONSOLE_PORT, '\r'); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 178 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 179 | pl01x_putc (CONSOLE_PORT, c); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 180 | } |
| 181 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 182 | static int pl01x_serial_getc(void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 183 | { |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 184 | return pl01x_getc (CONSOLE_PORT); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 187 | static int pl01x_serial_tstc(void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 188 | { |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 189 | return pl01x_tstc (CONSOLE_PORT); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 190 | } |
| 191 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 192 | static void pl01x_serial_setbrg(void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 193 | { |
Linus Walleij | 96baa4c | 2011-10-02 11:52:52 +0000 | [diff] [blame] | 194 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
| 195 | |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 196 | baudrate = gd->baudrate; |
Linus Walleij | 96baa4c | 2011-10-02 11:52:52 +0000 | [diff] [blame] | 197 | /* |
| 198 | * Flush FIFO and wait for non-busy before changing baudrate to avoid |
| 199 | * crap in console |
| 200 | */ |
| 201 | while (!(readl(®s->fr) & UART_PL01x_FR_TXFE)) |
| 202 | WATCHDOG_RESET(); |
| 203 | while (readl(®s->fr) & UART_PL01x_FR_BUSY) |
| 204 | WATCHDOG_RESET(); |
Matt Waddel | 249d521 | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 205 | serial_init(); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 206 | } |
| 207 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 208 | static void pl01x_putc (int portnum, char c) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 209 | { |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 210 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
| 211 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 212 | /* Wait until there is space in the FIFO */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 213 | while (readl(®s->fr) & UART_PL01x_FR_TXFF) |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 214 | WATCHDOG_RESET(); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 215 | |
| 216 | /* Send the character */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 217 | writel(c, ®s->dr); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 218 | } |
| 219 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 220 | static int pl01x_getc (int portnum) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 221 | { |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 222 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 223 | unsigned int data; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 224 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 225 | /* Wait until there is data in the FIFO */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 226 | while (readl(®s->fr) & UART_PL01x_FR_RXFE) |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 227 | WATCHDOG_RESET(); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 228 | |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 229 | data = readl(®s->dr); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 230 | |
| 231 | /* Check for an error flag */ |
| 232 | if (data & 0xFFFFFF00) { |
| 233 | /* Clear the error */ |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 234 | writel(0xFFFFFFFF, ®s->ecr); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 235 | return -1; |
| 236 | } |
| 237 | |
| 238 | return (int) data; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 239 | } |
| 240 | |
Andreas Engel | 20c9226 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 241 | static int pl01x_tstc (int portnum) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 242 | { |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 243 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
| 244 | |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 245 | WATCHDOG_RESET(); |
Rabin Vincent | 72d5e44 | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 246 | return !(readl(®s->fr) & UART_PL01x_FR_RXFE); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 247 | } |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 248 | |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 249 | static struct serial_device pl01x_serial_drv = { |
| 250 | .name = "pl01x_serial", |
| 251 | .start = pl01x_serial_init, |
| 252 | .stop = NULL, |
| 253 | .setbrg = pl01x_serial_setbrg, |
| 254 | .putc = pl01x_serial_putc, |
Marek Vasut | ec3fd68 | 2012-10-06 14:07:02 +0000 | [diff] [blame] | 255 | .puts = default_serial_puts, |
Marek Vasut | 39f6147 | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 256 | .getc = pl01x_serial_getc, |
| 257 | .tstc = pl01x_serial_tstc, |
| 258 | }; |
| 259 | |
| 260 | void pl01x_serial_initialize(void) |
| 261 | { |
| 262 | serial_register(&pl01x_serial_drv); |
| 263 | } |
| 264 | |
| 265 | __weak struct serial_device *default_serial_console(void) |
| 266 | { |
| 267 | return &pl01x_serial_drv; |
| 268 | } |