blob: 3e1713247d34c13cb052be830ae5706b529070b9 [file] [log] [blame]
Matthias Fuchs99d8b232009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs99d8b232009-07-22 13:56:21 +02006 */
7
8#include <common.h>
9#include <libfdt.h>
10#include <fdt_support.h>
11#include <asm/processor.h>
12#include <asm/io.h>
Stefan Roese09887762010-09-16 14:30:37 +020013#include <asm/ppc4xx-gpio.h>
Matthias Fuchs99d8b232009-07-22 13:56:21 +020014#include <asm/4xx_pci.h>
15#include <command.h>
16#include <malloc.h>
17
18/*
19 * PMC405-DE cpld registers
20 * - all registers are 8 bit
21 * - all registers are on 32 bit addesses
22 */
23struct pmc405de_cpld {
24 /* cpld design version */
25 u8 version;
26 u8 reserved0[3];
27
28 /* misc. status lines */
29 u8 status;
30 u8 reserved1[3];
31
32 /*
33 * gated control flags
34 * gate bit(s) must be written with '1' to
35 * access control flag
36 */
37 u8 control;
38 u8 reserved2[3];
39};
40
41#define CPLD_VERSION_MASK 0x0f
42#define CPLD_CONTROL_POSTLED_N 0x01
43#define CPLD_CONTROL_POSTLED_GATE 0x02
44#define CPLD_CONTROL_RESETOUT_N 0x40
45#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
46
47DECLARE_GLOBAL_DATA_PTR;
48
49extern void __ft_board_setup(void *blob, bd_t *bd);
50extern void pll_write(u32 a, u32 b);
51
52static int wait_for_pci_ready_done;
53
54static int is_monarch(void);
55static int pci_is_66mhz(void);
56static int board_revision(void);
57static int cpld_revision(void);
58static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
59
60int board_early_init_f(void)
61{
62 u32 pllmr0, pllmr1;
63
64 /*
65 * check M66EN and patch PLB:PCI divider for 66MHz PCI
66 *
67 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
68 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
69 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
70 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
71 *
72 * calling upd_plb_pci_div() may end in calling pll_write() which will
73 * do a chip reset and never return.
74 */
75 pllmr0 = mfdcr(CPC0_PLLMR0);
76 pllmr1 = mfdcr(CPC0_PLLMR1);
77
78 if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
79 /* fCPU=333MHz, fPLB=111MHz */
80 if (pci_is_66mhz())
81 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
82 else
83 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
84 } else {
85 /* fCPU=133|266MHz, fPLB=133MHz */
86 if (pci_is_66mhz())
87 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
88 else
89 upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
90 }
91
92 /*
93 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
94 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
95 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
96 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
97 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
98 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
99 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
100 */
Stefan Roese952e7762009-09-24 09:55:50 +0200101 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
102 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
103 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
104 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
105 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
106 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
107 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200108
109 /*
110 * EBC Configuration Register:
111 * - set ready timeout to 512 ebc-clks -> ca. 15 us
112 * - EBC lines are always driven
113 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200114 mtebc(EBC0_CFG, 0xa8400000);
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200115
116 return 0;
117}
118
119static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
120{
121 if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
122 pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
123}
124
125int misc_init_r(void)
126{
127 int i;
128 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
129 struct pmc405de_cpld *cpld =
130 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
131
132 if (!is_monarch()) {
133 /* PCI configuration done: release EREADY */
134 setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
135 setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
136 }
137
138 /* turn off POST LED */
139 out_8(&cpld->control,
140 CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
141
142 /* turn on LEDs: RUN, A, B */
143 clrbits_be32(&gpio0->or,
144 CONFIG_SYS_GPIO_LEDRUN_N |
145 CONFIG_SYS_GPIO_LEDA_N |
146 CONFIG_SYS_GPIO_LEDB_N);
147
148 for (i=0; i < 200; i++)
149 udelay(1000);
150
151 /* turn off LEDs: A, B */
152 setbits_be32(&gpio0->or,
153 CONFIG_SYS_GPIO_LEDA_N |
154 CONFIG_SYS_GPIO_LEDB_N);
155
156 return (0);
157}
158
159static int is_monarch(void)
160{
161 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
162 return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
163}
164
165static int pci_is_66mhz(void)
166{
167 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
168 return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
169}
170
171static int board_revision(void)
172{
173 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
174 return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
175 CONFIG_SYS_GPIO_HWREV_SHIFT);
176}
177
178static int cpld_revision(void)
179{
180 struct pmc405de_cpld *cpld =
181 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
182 return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
183}
184
185/*
186 * Check Board Identity
187 */
188int checkboard(void)
189{
190 puts("Board: esd GmbH - PMC-CPU/405-DE");
191
192 gd->board_type = board_revision();
193 printf(", Rev 1.%ld, ", gd->board_type);
194
195 if (!is_monarch())
196 puts("non-");
197
198 printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
199 pci_is_66mhz() ? "66" : "33", cpld_revision());
200
201 return 0;
202}
203
204
205static void wait_for_pci_ready(void)
206{
207 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
208 int i;
209 char *s = getenv("pcidelay");
210
211 /* only wait once */
212 if (wait_for_pci_ready_done)
213 return;
214
215 /*
216 * We have our own handling of the pcidelay variable.
217 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
218 * and adapter devices. For adapter devices we do not
219 * want this.
220 */
221 if (s) {
222 int ms = simple_strtoul(s, NULL, 10);
223 printf("PCI: Waiting for %d ms\n", ms);
224 for (i=0; i<ms; i++)
225 udelay(1000);
226 }
227
228 if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
229 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
230 while (1) {
231 if (ctrlc()) {
232 puts("abort\n");
233 break;
234 }
235 if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
236 printf("done\n");
237 break;
238 }
239 }
240 }
241
242 wait_for_pci_ready_done = 1;
243}
244
245/*
246 * Overwrite weak is_pci_host()
247 *
248 * This routine is called to determine if a pci scan should be
249 * performed. With various hardware environments (especially cPCI and
250 * PPMC) it's insufficient to depend on the state of the arbiter enable
251 * bit in the strap register, or generic host/adapter assumptions.
252 *
253 * Return 0 for adapter mode, non-zero for host (monarch) mode.
254 */
255int is_pci_host(struct pci_controller *hose)
256{
257 char *s;
258
259 if (!is_monarch()) {
260 /*
261 * Overwrite PCI identification when running in
262 * non-monarch mode
263 * This should be moved into pci_target_init()
264 * when it is sometimes available for 405 CPUs
265 */
266 pci_write_config_word(PCIDEVID_405GP,
267 PCI_SUBSYSTEM_ID,
268 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
269 pci_write_config_word(PCIDEVID_405GP,
270 PCI_CLASS_SUB_CODE,
271 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
272 }
273
274 s = getenv("pciscan");
275 if (s == NULL) {
276 if (is_monarch()) {
277 wait_for_pci_ready();
278 return 1;
279 } else {
280 return 0;
281 }
282 } else {
283 if (!strcmp(s, "yes"))
284 return 1;
285 }
286
287 return 0;
288}
289
290/*
291 * Overwrite weak pci_pre_init()
292 *
293 * The default implementation enables the 405EP
294 * internal PCI arbiter. We do not want that
295 * on a PMC module.
296 */
297int pci_pre_init(struct pci_controller *hose)
298{
299 return 1;
300}
301
302#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600303int ft_board_setup(void *blob, bd_t *bd)
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200304{
305 int rc;
306
307 __ft_board_setup(blob, bd);
308
309 /*
310 * Disable PCI in non-monarch mode.
311 */
312 if (!is_monarch()) {
313 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
314 "disabled", sizeof("disabled"), 1);
315 if (rc) {
316 printf("Unable to update property status in PCI node, "
317 "err=%s\n",
318 fdt_strerror(rc));
319 }
320 }
Simon Glasse895a4b2014-10-23 18:58:47 -0600321
322 return 0;
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200323}
324#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
325
326#if defined(CONFIG_SYS_EEPROM_WREN)
327/* Input: <dev_addr> I2C address of EEPROM device to enable.
328 * <state> -1: deliver current state
329 * 0: disable write
330 * 1: enable write
331 * Returns: -1: wrong device address
332 * 0: dis-/en- able done
333 * 0/1: current state if <state> was -1.
334 */
335int eeprom_write_enable(unsigned dev_addr, int state)
336{
337 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
338
339 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
340 return -1;
341 } else {
342 switch (state) {
343 case 1:
344 /* Enable write access, clear bit GPIO0. */
345 clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
346 state = 0;
347 break;
348 case 0:
349 /* Disable write access, set bit GPIO0. */
350 setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
351 state = 0;
352 break;
353 default:
354 /* Read current status back. */
355 state = (0 == (in_be32(&gpio0->or) &
356 CONFIG_SYS_GPIO_EEPROM_WP));
357 break;
358 }
359 }
360 return state;
361}
362
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200363int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200364{
365 int query = argc == 1;
366 int state = 0;
367
368 if (query) {
369 /* Query write access state. */
370 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
371 if (state < 0) {
372 puts("Query of write access state failed.\n");
373 } else {
374 printf("Write access for device 0x%0x is %sabled.\n",
375 CONFIG_SYS_I2C_EEPROM_ADDR,
376 state ? "en" : "dis");
377 state = 0;
378 }
379 } else {
380 if ('0' == argv[1][0]) {
381 /* Disable write access. */
382 state = eeprom_write_enable(
383 CONFIG_SYS_I2C_EEPROM_ADDR, 0);
384 } else {
385 /* Enable write access. */
386 state = eeprom_write_enable(
387 CONFIG_SYS_I2C_EEPROM_ADDR, 1);
388 }
389 if (state < 0)
390 puts ("Setup of write access state failed.\n");
391 }
392
393 return state;
394}
395
396U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
397 "Enable / disable / query EEPROM write access",
398 ""
399);
400#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
401
402#if defined(CONFIG_PRAM)
403#include <environment.h>
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200404
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200405int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200406{
407 u32 pram, nextbase, base;
408 char *v;
409 u32 param;
410 ulong *lptr;
411
412 v = getenv("pram");
413 if (v)
414 pram = simple_strtoul(v, NULL, 10);
415 else {
416 printf("Error: pram undefined. Please define pram in KiB\n");
417 return 1;
418 }
419
420 base = gd->bd->bi_memsize;
421#if defined(CONFIG_LOGBUFFER)
422 base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
423#endif
424 /*
425 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
426 */
427 param = base - (pram << 10);
428 printf("PARAM: @%08x\n", param);
Marek Vasut9cf5dee2011-10-21 14:17:22 +0000429 debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200430
431 /* clear entire PA ram */
432 memset((void*)param, 0, (pram << 10));
433
434 /* reserve 4k for pointer field */
435 nextbase = base - 4096;
436 lptr = (ulong*)(base);
437
438 /*
439 * *(--lptr) = item_size;
440 * *(--lptr) = base - item_base = distance from field top;
441 */
442
443 /* env is first (4k aligned) */
444 nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
445 memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
446 *(--lptr) = CONFIG_ENV_SIZE; /* size */
447 *(--lptr) = base - nextbase; /* offset | type=0 */
448
449 /* free section */
450 *(--lptr) = nextbase - param; /* size */
451 *(--lptr) = (base - param) | 126; /* offset | type=126 */
452
453 /* terminate pointer field */
454 *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
455 *(--lptr) = 0; /* offset=0 -> terminator */
456 return 0;
457}
458U_BOOT_CMD(
459 painit, 1, 1, do_painit,
460 "prepare PciAccess system",
461 ""
462);
463#endif /* CONFIG_PRAM */
464
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200465int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200466{
467 struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
468 setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
469 return 0;
470}
471U_BOOT_CMD(
472 selfreset, 1, 1, do_selfreset,
473 "assert self-reset# signal",
474 ""
475);
476
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200477int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200478{
479 struct pmc405de_cpld *cpld =
480 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
481
482 if (argc > 1) {
483 if (argv[1][0] == '0') {
484 /* assert */
485 printf("PMC-RESETOUT# asserted\n");
486 out_8(&cpld->control,
487 CPLD_CONTROL_RESETOUT_N_GATE);
488 } else {
489 /* deassert */
490 printf("PMC-RESETOUT# deasserted\n");
491 out_8(&cpld->control,
492 CPLD_CONTROL_RESETOUT_N |
493 CPLD_CONTROL_RESETOUT_N_GATE);
494 }
495 } else {
496 printf("PMC-RESETOUT# is %s\n",
497 (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
498 "inactive" : "active");
499 }
500 return 0;
501}
502U_BOOT_CMD(
503 resetout, 2, 1, do_resetout,
504 "assert PMC-RESETOUT# signal",
505 ""
506);