blob: e409cc3896d793909c8ba67390d2856ec100640a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stephen Warren10a03382016-05-12 13:32:56 -06002/*
3 * Copyright (c) 2013-2016, NVIDIA CORPORATION.
Stephen Warren10a03382016-05-12 13:32:56 -06004 */
5
6#ifndef _P2771_0000_H
7#define _P2771_0000_H
8
9#include <linux/sizes.h>
10
11#include "tegra186-common.h"
12
13/* High-level configuration options */
Tom Rinie660e972022-12-04 10:13:58 -050014#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
Stephen Warren10a03382016-05-12 13:32:56 -060015
Stephen Warren10a03382016-05-12 13:32:56 -060016/* Environment in eMMC, at the end of 2nd "boot sector" */
Stephen Warren10a03382016-05-12 13:32:56 -060017
Stephen Warrene43effc2018-01-08 17:41:25 -070018#define BOARD_EXTRA_ENV_SETTINGS \
19 "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
20 "ramdisk_addr_r\0" \
21 "kernel_addr_r_align=00200000\0" \
22 "kernel_addr_r_offset=00080000\0" \
23 "kernel_addr_r_size=02000000\0" \
24 "kernel_addr_r_aliases=loadaddr\0" \
25 "fdt_addr_r_align=00200000\0" \
26 "fdt_addr_r_offset=00000000\0" \
27 "fdt_addr_r_size=00200000\0" \
28 "scriptaddr_align=00200000\0" \
29 "scriptaddr_offset=00000000\0" \
30 "scriptaddr_size=00200000\0" \
31 "pxefile_addr_r_align=00200000\0" \
32 "pxefile_addr_r_offset=00000000\0" \
33 "pxefile_addr_r_size=00200000\0" \
34 "ramdisk_addr_r_align=00200000\0" \
35 "ramdisk_addr_r_offset=00000000\0" \
36 "ramdisk_addr_r_size=02000000\0"
37
Stephen Warren10a03382016-05-12 13:32:56 -060038#include "tegra-common-post.h"
39
Stephen Warren10a03382016-05-12 13:32:56 -060040#endif