blob: 152a0774fc0f2d0ac27330efb9eaa8c28ffaf174 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Valentin Longchampb7373372012-08-16 01:17:26 +00002/*
3 * (C) Copyright 2012
4 * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
Valentin Longchampb7373372012-08-16 01:17:26 +00005 */
6
7#ifndef __MV886352_H
8#define __MV886352_H
9
Valentin Longchampb7373372012-08-16 01:17:26 +000010
11/* PHY registers */
12#define PHY(itf) (itf)
13
14#define PHY_CTRL 0x00
15#define PHY_100_MBPS 0x2000
16#define PHY_1_GBPS 0x0040
17#define AUTONEG_EN 0x1000
18#define AUTONEG_RST 0x0200
19#define FULL_DUPLEX 0x0100
20#define PHY_PWR_DOWN 0x0800
21
22#define PHY_STATUS 0x01
23#define AN1000FIX 0x0001
24
25#define PHY_SPEC_CTRL 0x10
26#define SPEC_PWR_DOWN 0x0004
27#define AUTO_MDIX_EN 0x0060
28
29#define PHY_1000_CTRL 0x9
30
31#define NO_ADV 0x0000
32#define ADV_1000_FDPX 0x0200
33#define ADV_1000_HDPX 0x0100
34
35#define PHY_PAGE 0x16
36
37#define AN1000FIX_PAGE 0x00fc
38
39/* PORT or MAC registers */
40#define PORT(itf) (itf+0x10)
41
42#define PORT_STATUS 0x00
43#define NO_PHY_DETECT 0x0000
44
45#define PORT_PHY 0x01
46#define RX_RGMII_TIM 0x8000
47#define TX_RGMII_TIM 0x4000
48#define FLOW_CTRL_EN 0x0080
49#define FLOW_CTRL_FOR 0x0040
50#define LINK_VAL 0x0020
51#define LINK_FOR 0x0010
52#define FULL_DPX 0x0008
53#define FULL_DPX_FOR 0x0004
54#define NO_SPEED_FOR 0x0003
55#define SPEED_1000_FOR 0x0002
56#define SPEED_100_FOR 0x0001
57#define SPEED_10_FOR 0x0000
58
59#define PORT_CTRL 0x04
60#define FORWARDING 0x0003
61#define EGRS_FLD_ALL 0x000c
62#define PORT_DIS 0x0000
63
64struct mv88e_sw_reg {
65 u8 port;
66 u8 reg;
67 u16 value;
68};
69
70int mv88e_sw_reset(const char *devname, u8 phy_addr);
71int mv88e_sw_program(const char *devname, u8 phy_addr,
72 struct mv88e_sw_reg *regs, int regs_nb);
73
74#endif