blob: c55d6107a49af6d7897f564007a6ff53541cafe5 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Maciej W. Rozyckia398a512021-11-20 23:03:30 +00008 * Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
wdenkc6097192002-11-03 00:24:07 +00009 */
10
11#ifndef _PCI_H
12#define _PCI_H
13
Minghuan Lianed5b5802015-07-10 11:35:08 +080014#define PCI_CFG_SPACE_SIZE 256
15#define PCI_CFG_SPACE_EXP_SIZE 4096
16
wdenkc6097192002-11-03 00:24:07 +000017/*
18 * Under PCI, each device has 256 bytes of configuration address space,
19 * of which the first 64 bytes are standardized as follows:
20 */
Bin Mengdac01fd2018-08-03 01:14:52 -070021#define PCI_STD_HEADER_SIZEOF 64
wdenkc6097192002-11-03 00:24:07 +000022#define PCI_VENDOR_ID 0x00 /* 16 bits */
23#define PCI_DEVICE_ID 0x02 /* 16 bits */
24#define PCI_COMMAND 0x04 /* 16 bits */
25#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
26#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
27#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
28#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
29#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
30#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
31#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
32#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
33#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
34#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
35
36#define PCI_STATUS 0x06 /* 16 bits */
37#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
38#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
39#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
40#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
41#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
42#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
43#define PCI_STATUS_DEVSEL_FAST 0x000
44#define PCI_STATUS_DEVSEL_MEDIUM 0x200
45#define PCI_STATUS_DEVSEL_SLOW 0x400
46#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
47#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
48#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
49#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
50#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
51
52#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
53 revision */
54#define PCI_REVISION_ID 0x08 /* Revision ID */
55#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
56#define PCI_CLASS_DEVICE 0x0a /* Device class */
57#define PCI_CLASS_CODE 0x0b /* Device class code */
58#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
59
60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62#define PCI_HEADER_TYPE 0x0e /* 8 bits */
63#define PCI_HEADER_TYPE_NORMAL 0
64#define PCI_HEADER_TYPE_BRIDGE 1
65#define PCI_HEADER_TYPE_CARDBUS 2
66
67#define PCI_BIST 0x0f /* 8 bits */
68#define PCI_BIST_CODE_MASK 0x0f /* Return result */
69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72/*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85#define PCI_BASE_ADDRESS_SPACE_IO 0x01
86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Gala30e76d52008-10-21 08:36:08 -050092#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
93#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +000094/* bit 1 is reserved if address_space = 1 */
95
Simon Glass37a1cf92019-09-25 08:56:06 -060096/* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
97#define pci_offset_to_barnum(offset) \
98 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
99
wdenkc6097192002-11-03 00:24:07 +0000100/* Header type 0 (normal devices) */
101#define PCI_CARDBUS_CIS 0x28
102#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
103#define PCI_SUBSYSTEM_ID 0x2e
104#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
105#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Gala30e76d52008-10-21 08:36:08 -0500106#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000107
108#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
109
110/* 0x35-0x3b are reserved */
111#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
112#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
113#define PCI_MIN_GNT 0x3e /* 8 bits */
114#define PCI_MAX_LAT 0x3f /* 8 bits */
115
Simon Glass5f48d792015-07-27 15:47:17 -0600116#define PCI_INTERRUPT_LINE_DISABLE 0xff
117
wdenkc6097192002-11-03 00:24:07 +0000118/* Header type 1 (PCI-to-PCI bridges) */
119#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
120#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
121#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
122#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
123#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
124#define PCI_IO_LIMIT 0x1d
125#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
126#define PCI_IO_RANGE_TYPE_16 0x00
127#define PCI_IO_RANGE_TYPE_32 0x01
128#define PCI_IO_RANGE_MASK ~0x0f
129#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
130#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
131#define PCI_MEMORY_LIMIT 0x22
132#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
133#define PCI_MEMORY_RANGE_MASK ~0x0f
134#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
135#define PCI_PREF_MEMORY_LIMIT 0x26
136#define PCI_PREF_RANGE_TYPE_MASK 0x0f
137#define PCI_PREF_RANGE_TYPE_32 0x00
138#define PCI_PREF_RANGE_TYPE_64 0x01
139#define PCI_PREF_RANGE_MASK ~0x0f
140#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
141#define PCI_PREF_LIMIT_UPPER32 0x2c
142#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
143#define PCI_IO_LIMIT_UPPER16 0x32
144/* 0x34 same as for htype 0 */
145/* 0x35-0x3b is reserved */
146#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
147/* 0x3c-0x3d are same as for htype 0 */
148#define PCI_BRIDGE_CONTROL 0x3e
149#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
150#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
151#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
152#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
153#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
154#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
155#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
156
157/* Header type 2 (CardBus bridges) */
158#define PCI_CB_CAPABILITY_LIST 0x14
159/* 0x15 reserved */
160#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
161#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
162#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
163#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
164#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
165#define PCI_CB_MEMORY_BASE_0 0x1c
166#define PCI_CB_MEMORY_LIMIT_0 0x20
167#define PCI_CB_MEMORY_BASE_1 0x24
168#define PCI_CB_MEMORY_LIMIT_1 0x28
169#define PCI_CB_IO_BASE_0 0x2c
170#define PCI_CB_IO_BASE_0_HI 0x2e
171#define PCI_CB_IO_LIMIT_0 0x30
172#define PCI_CB_IO_LIMIT_0_HI 0x32
173#define PCI_CB_IO_BASE_1 0x34
174#define PCI_CB_IO_BASE_1_HI 0x36
175#define PCI_CB_IO_LIMIT_1 0x38
176#define PCI_CB_IO_LIMIT_1_HI 0x3a
177#define PCI_CB_IO_RANGE_MASK ~0x03
178/* 0x3c-0x3d are same as for htype 0 */
179#define PCI_CB_BRIDGE_CONTROL 0x3e
180#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
181#define PCI_CB_BRIDGE_CTL_SERR 0x02
182#define PCI_CB_BRIDGE_CTL_ISA 0x04
183#define PCI_CB_BRIDGE_CTL_VGA 0x08
184#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
185#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
186#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
187#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
188#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
189#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
190#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
191#define PCI_CB_SUBSYSTEM_ID 0x42
192#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
193/* 0x48-0x7f reserved */
194
195/* Capability lists */
196
197#define PCI_CAP_LIST_ID 0 /* Capability ID */
198#define PCI_CAP_ID_PM 0x01 /* Power Management */
199#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
200#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
201#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
202#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
203#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Bin Meng5d544f92018-08-03 01:14:51 -0700204#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
205#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
206#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
207#define PCI_CAP_ID_DBG 0x0A /* Debug port */
208#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
209#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
210#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
211#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
212#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
213#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
214#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
215#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
216#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
217#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
218#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
wdenkc6097192002-11-03 00:24:07 +0000219#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
220#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
221#define PCI_CAP_SIZEOF 4
222
223/* Power Management Registers */
224
225#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
226#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
227#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
228#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
229#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
230#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
231#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
232#define PCI_PM_CTRL 4 /* PM control and status register */
233#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
234#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
235#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
236#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
237#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
238#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
239#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
240#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
241#define PCI_PM_DATA_REGISTER 7 /* (??) */
242#define PCI_PM_SIZEOF 8
243
244/* AGP registers */
245
246#define PCI_AGP_VERSION 2 /* BCD version number */
247#define PCI_AGP_RFU 3 /* Rest of capability flags */
248#define PCI_AGP_STATUS 4 /* Status register */
249#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
250#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
251#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
252#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
253#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
254#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
255#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
256#define PCI_AGP_COMMAND 8 /* Control register */
257#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
258#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
259#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
260#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
261#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
262#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
263#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
264#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
265#define PCI_AGP_SIZEOF 12
266
Matthew McClintockf0e6f572006-06-28 10:44:49 -0500267/* PCI-X registers */
268
269#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
270#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
271#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
272#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
273#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
274
275
wdenkc6097192002-11-03 00:24:07 +0000276/* Slot Identification */
277
278#define PCI_SID_ESR 2 /* Expansion Slot Register */
279#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
280#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
281#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
282
283/* Message Signalled Interrupts registers */
284
285#define PCI_MSI_FLAGS 2 /* Various flags */
286#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
287#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
288#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
289#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
Ramon Fried8781d042019-04-06 05:12:01 +0300290#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
wdenkc6097192002-11-03 00:24:07 +0000291#define PCI_MSI_RFU 3 /* Rest of capability flags */
292#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
293#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
294#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
295#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
296
297#define PCI_MAX_PCI_DEVICES 32
298#define PCI_MAX_PCI_FUNCTIONS 8
299
Zhao Qiang287df012013-10-12 13:46:33 +0800300#define PCI_FIND_CAP_TTL 0x48
301#define CAP_START_POS 0x40
302
Minghuan Lianed5b5802015-07-10 11:35:08 +0800303/* Extended Capabilities (PCI-X 2.0 and Express) */
304#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
305#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
306#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
307
308#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
309#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
310#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
311#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
312#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
313#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
314#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
315#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
316#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
317#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
318#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
319#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
320#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
321#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
322#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
323#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
324#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
325#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
326#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
327#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
328#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
329#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
330#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
331#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
332#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
333#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
334#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
Bin Meng5d544f92018-08-03 01:14:51 -0700335#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
336#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
337#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
338#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
Minghuan Lianed5b5802015-07-10 11:35:08 +0800339
Alex Marginean0b143d82019-06-07 11:24:23 +0300340/* Enhanced Allocation Registers */
341#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
342#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
343#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
344#define PCI_EA_ES 0x00000007 /* Entry Size */
345#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
Suneel Garapati51eeae92019-10-19 16:34:16 -0700346/* 9-14 map to VF BARs 0-5 respectively */
347#define PCI_EA_BEI_VF_BAR0 9
348#define PCI_EA_BEI_VF_BAR5 14
Alex Marginean0b143d82019-06-07 11:24:23 +0300349/* Base, MaxOffset registers */
350/* bit 0 is reserved */
351#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
352#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
353
Alex Margineanb8e1f822019-06-07 11:24:25 +0300354/* PCI Express capabilities */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200355#define PCI_EXP_FLAGS 2 /* Capabilities register */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000356#define PCI_EXP_FLAGS_VERS 0x000f /* Capability Version */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200357#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000358#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
359#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
360#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
Alex Margineanb8e1f822019-06-07 11:24:25 +0300361#define PCI_EXP_DEVCAP 4 /* Device capabilities */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200362#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
Alex Margineanb8e1f822019-06-07 11:24:25 +0300363#define PCI_EXP_DEVCTL 8 /* Device Control */
Pali Rohár819a43c2022-02-10 14:53:42 +0100364#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
365#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
366#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
367#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
368#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
369#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
370#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
371#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
372#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
373#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
374#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
375#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
376#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
377#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
378#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
379#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200380#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
381#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
Sylwester Nawrockidb754852020-05-25 13:39:57 +0200382#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000383#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
384#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
385#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
Sylwester Nawrockidb754852020-05-25 13:39:57 +0200386#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200387#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000388#define PCI_EXP_LNKCTL 16 /* Link Control */
389#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200390#define PCI_EXP_LNKSTA 18 /* Link Status */
Sylwester Nawrockidb754852020-05-25 13:39:57 +0200391#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
392#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
393#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
394#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
395#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
396#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000397#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200398#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000399#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
Sylwester Nawrockib6687e12020-05-25 13:39:53 +0200400#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
401#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
Pali Rohár1d7ad682021-09-26 00:54:44 +0200402#define PCI_EXP_RTCTL 28 /* Root Control */
403#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
404#define PCI_EXP_RTCAP 30 /* Root Capabilities */
405#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
Laurentiu Tudor284d0622020-09-10 12:42:18 +0300406#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
407#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
408#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
409#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000410#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
411#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
Sylwester Nawrockidb754852020-05-25 13:39:57 +0200412#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
Maciej W. Rozyckia398a512021-11-20 23:03:30 +0000413#define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */
414#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Target Link Speed 2.5GT/s */
415#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
416#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
417
Pali Rohár819a43c2022-02-10 14:53:42 +0100418/* Advanced Error Reporting */
419#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
420#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
421#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
422#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
423#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
424#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
425
Suneel Garapatib8852dc2019-10-19 16:07:20 -0700426/* Single Root I/O Virtualization Registers */
427#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
428#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
429#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
430#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
Laurentiu Tudor284d0622020-09-10 12:42:18 +0300431#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
Suneel Garapatib8852dc2019-10-19 16:07:20 -0700432#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
433#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
434#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
435#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
436#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
437#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
Alex Margineanb8e1f822019-06-07 11:24:25 +0300438
wdenkc6097192002-11-03 00:24:07 +0000439/* Include the ID list */
440
441#include <pci_ids.h>
442
Pali Rohára4bc38d2021-11-03 01:01:05 +0100443/*
Pali Rohár2a8d4022021-11-26 11:42:41 +0100444 * Config Address for PCI Configuration Mechanism #1
445 *
446 * See PCI Local Bus Specification, Revision 3.0,
447 * Section 3.2.2.3.2, Figure 3-2, p. 50.
448 */
449
450#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
451#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
452#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
453
454#define PCI_CONF1_BUS_MASK 0xff
455#define PCI_CONF1_DEV_MASK 0x1f
456#define PCI_CONF1_FUNC_MASK 0x7
457#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
458
459#define PCI_CONF1_ENABLE BIT(31)
460#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
461#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
462#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
463#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
464
465#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
466 (PCI_CONF1_ENABLE | \
467 PCI_CONF1_BUS(bus) | \
468 PCI_CONF1_DEV(dev) | \
469 PCI_CONF1_FUNC(func) | \
470 PCI_CONF1_REG(reg))
471
472/*
473 * Extension of PCI Config Address for accessing extended PCIe registers
474 *
475 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
476 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
477 * are used for specifying additional 4 high bits of PCI Express register.
478 */
479
480#define PCI_CONF1_EXT_REG_SHIFT 16
481#define PCI_CONF1_EXT_REG_MASK 0xf00
482#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
483
484#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
485 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
486 PCI_CONF1_EXT_REG(reg))
487
488/*
Pali Rohára4bc38d2021-11-03 01:01:05 +0100489 * Enhanced Configuration Access Mechanism (ECAM)
490 *
491 * See PCI Express Base Specification, Revision 5.0, Version 1.0,
492 * Section 7.2.2, Table 7-1, p. 677.
493 */
494#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
495#define PCIE_ECAM_DEV_SHIFT 15 /* Device number */
496#define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */
497
498#define PCIE_ECAM_BUS_MASK 0xff
499#define PCIE_ECAM_DEV_MASK 0x1f
500#define PCIE_ECAM_FUNC_MASK 0x7
501#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
502
503#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
504#define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT)
505#define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT)
506#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
507
508#define PCIE_ECAM_OFFSET(bus, dev, func, where) \
509 (PCIE_ECAM_BUS(bus) | \
510 PCIE_ECAM_DEV(dev) | \
511 PCIE_ECAM_FUNC(func) | \
512 PCIE_ECAM_REG(where))
513
Paul Burtonfa5cec02013-11-08 11:18:47 +0000514#ifndef __ASSEMBLY__
515
Simon Glass6dd4b012019-12-06 21:41:38 -0700516#include <dm/pci.h>
517
Kumar Gala30e76d52008-10-21 08:36:08 -0500518#ifdef CONFIG_SYS_PCI_64BIT
519typedef u64 pci_addr_t;
520typedef u64 pci_size_t;
521#else
Heinrich Schuchardt58fc2b52020-02-05 21:59:12 +0100522typedef unsigned long pci_addr_t;
523typedef unsigned long pci_size_t;
Kumar Gala30e76d52008-10-21 08:36:08 -0500524#endif
wdenkc6097192002-11-03 00:24:07 +0000525
Kumar Gala30e76d52008-10-21 08:36:08 -0500526struct pci_region {
527 pci_addr_t bus_start; /* Start on the bus */
528 phys_addr_t phys_start; /* Start in physical address space */
529 pci_size_t size; /* Size */
530 unsigned long flags; /* Resource flags */
531
532 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000533};
534
535#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
536#define PCI_REGION_IO 0x00000001 /* PCI IO space */
537#define PCI_REGION_TYPE 0x00000001
Kumar Galaa1790122006-01-11 13:24:15 -0600538#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000539
Kumar Galaff4e66e2009-02-06 09:49:31 -0600540#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000541#define PCI_REGION_RO 0x00000200 /* Read-only memory */
542
Simon Glassbc3442a2013-06-11 11:14:33 -0700543static inline void pci_set_region(struct pci_region *reg,
Kumar Gala30e76d52008-10-21 08:36:08 -0500544 pci_addr_t bus_start,
Becky Bruce36f32672008-05-07 13:24:57 -0500545 phys_addr_t phys_start,
Kumar Gala30e76d52008-10-21 08:36:08 -0500546 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000547 unsigned long flags) {
548 reg->bus_start = bus_start;
549 reg->phys_start = phys_start;
550 reg->size = size;
551 reg->flags = flags;
552}
553
554typedef int pci_dev_t;
555
Simon Glassff3e0772015-03-05 12:25:25 -0700556#define PCI_BUS(d) (((d) >> 16) & 0xff)
Stefan Roese2253d642019-02-11 08:43:25 +0100557
558/*
559 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
560 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
561 * Please see the Linux header include/uapi/linux/pci.h for more details.
562 * This is relevant for the following macros:
563 * PCI_DEV, PCI_FUNC, PCI_DEVFN
564 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
Simon Glass5f20c282020-05-10 10:26:54 -0600565 * the remark from above (input is in bits 15-8 instead of 7-0.
Stefan Roese2253d642019-02-11 08:43:25 +0100566 */
Simon Glassff3e0772015-03-05 12:25:25 -0700567#define PCI_DEV(d) (((d) >> 11) & 0x1f)
568#define PCI_FUNC(d) (((d) >> 8) & 0x7)
569#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
Stefan Roese2253d642019-02-11 08:43:25 +0100570
Simon Glassff3e0772015-03-05 12:25:25 -0700571#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
572#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
573#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
Simon Glassff3e0772015-03-05 12:25:25 -0700574#define PCI_ANY_ID (~0)
wdenkc6097192002-11-03 00:24:07 +0000575
Simon Glassf0597032020-04-08 08:32:59 -0600576/* Convert from Linux format to U-Boot format */
577#define PCI_TO_BDF(val) ((val) << 8)
578
wdenkc6097192002-11-03 00:24:07 +0000579struct pci_device_id {
Simon Glassaba92962015-07-06 16:47:44 -0600580 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
581 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
582 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
583 unsigned long driver_data; /* Data private to the driver */
wdenkc6097192002-11-03 00:24:07 +0000584};
585
586struct pci_controller;
587
588struct pci_config_table {
589 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
590 unsigned int class; /* Class ID, or PCI_ANY_ID */
591 unsigned int bus; /* Bus number, or PCI_ANY_ID */
592 unsigned int dev; /* Device number, or PCI_ANY_ID */
593 unsigned int func; /* Function number, or PCI_ANY_ID */
594
595 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
596 struct pci_config_table *);
597 unsigned long priv[3];
598};
599
Wolfgang Denk993a2272006-03-12 16:54:11 +0100600extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
601 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000602extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
603 struct pci_config_table *);
604
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300605#define INDIRECT_TYPE_NO_PCIE_LINK 1
606
Simon Glass2206ac22019-12-06 21:41:37 -0700607/**
wdenkc6097192002-11-03 00:24:07 +0000608 * Structure of a PCI controller (host bridge)
Simon Glass54fe7b12015-11-26 19:51:21 -0700609 *
610 * With driver model this is dev_get_uclass_priv(bus)
Simon Glass2206ac22019-12-06 21:41:37 -0700611 *
612 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
613 * relocated. Normally if PCI is used before relocation, this happens
614 * before relocation also. Some platforms set up static configuration in
615 * TPL/SPL to reduce code size and boot time, since these phases only know
616 * about a small subset of PCI devices. This is normally false.
wdenkc6097192002-11-03 00:24:07 +0000617 */
618struct pci_controller {
Simon Glassff3e0772015-03-05 12:25:25 -0700619 struct udevice *bus;
620 struct udevice *ctlr;
Simon Glass2206ac22019-12-06 21:41:37 -0700621 bool skip_auto_config_until_reloc;
wdenkc6097192002-11-03 00:24:07 +0000622
623 int first_busno;
624 int last_busno;
625
626 volatile unsigned int *cfg_addr;
627 volatile unsigned char *cfg_data;
628
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300629 int indirect_type;
630
Simon Glassaec241d2015-06-07 08:50:40 -0600631 /*
632 * TODO(sjg@chromium.org): With driver model we use struct
633 * pci_controller for both the controller and any bridge devices
634 * attached to it. But there is only one region list and it is in the
635 * top-level controller.
636 *
637 * This could be changed so that struct pci_controller is only used
638 * for PCI controllers and a separate UCLASS (or perhaps
639 * UCLASS_PCI_GENERIC) is used for bridges.
640 */
Stefan Roesee0024742020-07-23 16:34:10 +0200641 struct pci_region *regions;
wdenkc6097192002-11-03 00:24:07 +0000642 int region_count;
643
644 struct pci_config_table *config_table;
645
646 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
wdenkc6097192002-11-03 00:24:07 +0000647
648 /* Used by auto config */
Kumar Galaa1790122006-01-11 13:24:15 -0600649 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000650};
651
Simon Glass26543cc2021-08-01 18:54:16 -0600652#if defined(CONFIG_DM_PCI_COMPAT)
Becky Bruce36f32672008-05-07 13:24:57 -0500653extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Gala30e76d52008-10-21 08:36:08 -0500654 pci_addr_t addr, unsigned long flags);
655extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
656 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000657
658#define pci_phys_to_bus(dev, addr, flags) \
659 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
660#define pci_bus_to_phys(dev, addr, flags) \
661 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
662
Becky Bruce6e61fae2009-02-03 18:10:50 -0600663#define pci_virt_to_bus(dev, addr, flags) \
664 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
665 (virt_to_phys(addr)), (flags))
666#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
667 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
668 (addr), (flags)), \
669 (len), (map_flags))
670
671#define pci_phys_to_mem(dev, addr) \
672 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
673#define pci_mem_to_phys(dev, addr) \
674 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
675#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
676#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
677
678#define pci_virt_to_mem(dev, addr) \
679 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
680#define pci_mem_to_virt(dev, addr, len, map_flags) \
681 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
682#define pci_virt_to_io(dev, addr) \
683 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
684#define pci_io_to_virt(dev, addr, len, map_flags) \
685 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000686
Simon Glassdc5740d2015-08-22 15:58:55 -0600687/* For driver model these are defined in macros in pci_compat.c */
wdenkc6097192002-11-03 00:24:07 +0000688extern int pci_hose_read_config_byte(struct pci_controller *hose,
689 pci_dev_t dev, int where, u8 *val);
690extern int pci_hose_read_config_word(struct pci_controller *hose,
691 pci_dev_t dev, int where, u16 *val);
692extern int pci_hose_read_config_dword(struct pci_controller *hose,
693 pci_dev_t dev, int where, u32 *val);
694extern int pci_hose_write_config_byte(struct pci_controller *hose,
695 pci_dev_t dev, int where, u8 val);
696extern int pci_hose_write_config_word(struct pci_controller *hose,
697 pci_dev_t dev, int where, u16 val);
698extern int pci_hose_write_config_dword(struct pci_controller *hose,
699 pci_dev_t dev, int where, u32 val);
Simon Glass3ba5f742015-11-26 19:51:30 -0700700#endif
wdenkc6097192002-11-03 00:24:07 +0000701
Simon Glass3ba5f742015-11-26 19:51:30 -0700702void pciauto_region_init(struct pci_region *res);
703void pciauto_region_align(struct pci_region *res, pci_size_t size);
704void pciauto_config_init(struct pci_controller *hose);
Tuomas Tynkkynen5ce9aca2018-05-14 23:50:05 +0300705
706/**
707 * pciauto_region_allocate() - Allocate resources from a PCI resource region
708 *
709 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
710 * false, the result will be guaranteed to fit in 32 bits.
711 *
712 * @res: PCI region to allocate from
713 * @size: Amount of bytes to allocate
714 * @bar: Returns the PCI bus address of the allocated resource
715 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100716 * Return: 0 if successful, -1 on failure
Tuomas Tynkkynen5ce9aca2018-05-14 23:50:05 +0300717 */
Simon Glass3ba5f742015-11-26 19:51:30 -0700718int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300719 pci_addr_t *bar, bool supports_64bit);
Vladimir Oltean2649f692021-09-17 15:11:20 +0300720int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
Simon Glass3ba5f742015-11-26 19:51:30 -0700721
Simon Glass26543cc2021-08-01 18:54:16 -0600722#if defined(CONFIG_DM_PCI_COMPAT)
wdenkc6097192002-11-03 00:24:07 +0000723extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
724 pci_dev_t dev, int where, u8 *val);
725extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
726 pci_dev_t dev, int where, u16 *val);
727extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
728 pci_dev_t dev, int where, u8 val);
729extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
730 pci_dev_t dev, int where, u16 val);
731
Becky Bruce6e61fae2009-02-03 18:10:50 -0600732extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000733extern void pci_register_hose(struct pci_controller* hose);
734extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600735extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
Stuart Yodereeb5b1a2016-03-10 10:52:18 -0600736extern struct pci_controller *pci_get_hose_head(void);
wdenkc6097192002-11-03 00:24:07 +0000737
738extern int pci_hose_scan(struct pci_controller *hose);
739extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
740
wdenkc6097192002-11-03 00:24:07 +0000741extern void pciauto_setup_device(struct pci_controller *hose,
742 pci_dev_t dev, int bars_num,
743 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -0600744 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000745 struct pci_region *io);
Linus Walleija3a70722012-03-25 12:13:15 +0000746extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
747 pci_dev_t dev, int sub_bus);
748extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
749 pci_dev_t dev, int sub_bus);
Linus Walleija3a70722012-03-25 12:13:15 +0000750extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000751
752extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
753extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
Simon Glass250e0392015-01-27 22:13:27 -0700754pci_dev_t pci_find_class(unsigned int find_class, int index);
wdenkc6097192002-11-03 00:24:07 +0000755
Zhao Qiang287df012013-10-12 13:46:33 +0800756extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
757 int cap);
758extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
759 u8 hdr_type);
760extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
761 int cap);
762
Minghuan Lianed5b5802015-07-10 11:35:08 +0800763int pci_find_next_ext_capability(struct pci_controller *hose,
764 pci_dev_t dev, int start, int cap);
765int pci_hose_find_ext_capability(struct pci_controller *hose,
766 pci_dev_t dev, int cap);
767
Simon Glass26543cc2021-08-01 18:54:16 -0600768#endif /* defined(CONFIG_DM_PCI_COMPAT) */
Tim Harvey09918662014-08-07 22:49:56 -0700769
Peter Tyser983eb9d2010-10-29 17:59:27 -0500770const char * pci_class_str(u8 class);
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300771int pci_last_busno(void);
772
Jon Loeliger13a7fcd2006-10-19 11:33:52 -0500773#ifdef CONFIG_MPC85xx
774extern void pci_mpc85xx_init (struct pci_controller *hose);
775#endif
Paul Burtonfa5cec02013-11-08 11:18:47 +0000776
Simon Glasse8a552e2014-11-14 18:18:30 -0700777/**
778 * pci_write_bar32() - Write the address of a BAR including control bits
779 *
Simon Glass9d731c82016-01-18 20:19:15 -0700780 * This writes a raw address (with control bits) to a bar. This can be used
781 * with devices which require hard-coded addresses, not part of the normal
782 * PCI enumeration process.
Simon Glasse8a552e2014-11-14 18:18:30 -0700783 *
Simon Glasse8c09d62021-08-01 18:54:17 -0600784 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
785 *
Simon Glasse8a552e2014-11-14 18:18:30 -0700786 * @hose: PCI hose to use
787 * @dev: PCI device to update
788 * @barnum: BAR number (0-5)
789 * @addr: BAR address with control bits
790 */
791void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
Simon Glass9d731c82016-01-18 20:19:15 -0700792 u32 addr);
Simon Glasse8a552e2014-11-14 18:18:30 -0700793
794/**
795 * pci_read_bar32() - read the address of a bar
796 *
Simon Glasse8c09d62021-08-01 18:54:17 -0600797 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
798 *
Simon Glasse8a552e2014-11-14 18:18:30 -0700799 * @hose: PCI hose to use
800 * @dev: PCI device to inspect
801 * @barnum: BAR number (0-5)
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100802 * Return: address of the bar, masking out any control bits
Simon Glasse8a552e2014-11-14 18:18:30 -0700803 * */
804u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
805
Simon Glass4a2708a2015-01-14 21:37:04 -0700806/**
Simon Glassaab67242015-03-05 12:25:24 -0700807 * pci_hose_find_devices() - Find devices by vendor/device ID
808 *
Simon Glasse8c09d62021-08-01 18:54:17 -0600809 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
810 *
Simon Glassaab67242015-03-05 12:25:24 -0700811 * @hose: PCI hose to search
812 * @busnum: Bus number to search
813 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
814 * @indexp: Pointer to device index to find. To find the first matching
815 * device, pass 0; to find the second, pass 1, etc. This
816 * parameter is decremented for each non-matching device so
817 * can be called repeatedly.
818 */
819pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
820 struct pci_device_id *ids, int *indexp);
821
Simon Glassff3e0772015-03-05 12:25:25 -0700822/* Access sizes for PCI reads and writes */
823enum pci_size_t {
824 PCI_SIZE_8,
825 PCI_SIZE_16,
826 PCI_SIZE_32,
827};
828
829struct udevice;
830
Simon Glassff3e0772015-03-05 12:25:25 -0700831/**
Simon Glass8a8d24b2020-12-03 16:55:23 -0700832 * struct pci_child_plat - information stored about each PCI device
Simon Glassff3e0772015-03-05 12:25:25 -0700833 *
834 * Every device on a PCI bus has this per-child data.
835 *
Simon Glasscaa4daa2020-12-03 16:55:18 -0700836 * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a
Simon Glassff3e0772015-03-05 12:25:25 -0700837 * PCI bus (i.e. UCLASS_PCI)
838 *
839 * @devfn: Encoded device and function index - see PCI_DEVFN()
840 * @vendor: PCI vendor ID (see pci_ids.h)
841 * @device: PCI device ID (see pci_ids.h)
842 * @class: PCI class, 3 bytes: (base, sub, prog-if)
Suneel Garapatib8852dc2019-10-19 16:07:20 -0700843 * @is_virtfn: True for Virtual Function device
844 * @pfdev: Handle to Physical Function device
845 * @virtid: Virtual Function Index
Simon Glassff3e0772015-03-05 12:25:25 -0700846 */
Simon Glass8a8d24b2020-12-03 16:55:23 -0700847struct pci_child_plat {
Simon Glassff3e0772015-03-05 12:25:25 -0700848 int devfn;
849 unsigned short vendor;
850 unsigned short device;
851 unsigned int class;
Suneel Garapatib8852dc2019-10-19 16:07:20 -0700852
853 /* Variables for CONFIG_PCI_SRIOV */
854 bool is_virtfn;
855 struct udevice *pfdev;
856 int virtid;
Simon Glassff3e0772015-03-05 12:25:25 -0700857};
858
859/* PCI bus operations */
860struct dm_pci_ops {
861 /**
862 * read_config() - Read a PCI configuration value
863 *
864 * PCI buses must support reading and writing configuration values
865 * so that the bus can be scanned and its devices configured.
866 *
Simon Glass8b85dfc2020-12-16 21:20:07 -0700867 * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always.
Simon Glassff3e0772015-03-05 12:25:25 -0700868 * If bridges exist it is possible to use the top-level bus to
869 * access a sub-bus. In that case @bus will be the top-level bus
870 * and PCI_BUS(bdf) will be a different (higher) value
871 *
872 * @bus: Bus to read from
873 * @bdf: Bus, device and function to read
874 * @offset: Byte offset within the device's configuration space
875 * @valuep: Place to put the returned value
876 * @size: Access size
877 * @return 0 if OK, -ve on error
878 */
Simon Glassc4e72c42020-01-27 08:49:37 -0700879 int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
880 uint offset, ulong *valuep, enum pci_size_t size);
Simon Glassff3e0772015-03-05 12:25:25 -0700881 /**
882 * write_config() - Write a PCI configuration value
883 *
884 * @bus: Bus to write to
885 * @bdf: Bus, device and function to write
886 * @offset: Byte offset within the device's configuration space
887 * @value: Value to write
888 * @size: Access size
889 * @return 0 if OK, -ve on error
890 */
891 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
892 ulong value, enum pci_size_t size);
893};
894
895/* Get access to a PCI bus' operations */
896#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
897
898/**
Simon Glass21ccce12015-11-29 13:17:47 -0700899 * dm_pci_get_bdf() - Get the BDF value for a device
Simon Glass4b515e42015-07-06 16:47:46 -0600900 *
901 * @dev: Device to check
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100902 * Return: bus/device/function value (see PCI_BDF())
Simon Glass4b515e42015-07-06 16:47:46 -0600903 */
Simon Glass194fca92020-01-27 08:49:38 -0700904pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
Simon Glass4b515e42015-07-06 16:47:46 -0600905
906/**
Simon Glassff3e0772015-03-05 12:25:25 -0700907 * pci_bind_bus_devices() - scan a PCI bus and bind devices
908 *
909 * Scan a PCI bus looking for devices. Bind each one that is found. If
910 * devices are already bound that match the scanned devices, just update the
911 * child data so that the device can be used correctly (this happens when
912 * the device tree describes devices we expect to see on the bus).
913 *
914 * Devices that are bound in this way will use a generic PCI driver which
915 * does nothing. The device can still be accessed but will not provide any
916 * driver interface.
917 *
918 * @bus: Bus containing devices to bind
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100919 * Return: 0 if OK, -ve on error
Simon Glassff3e0772015-03-05 12:25:25 -0700920 */
921int pci_bind_bus_devices(struct udevice *bus);
922
923/**
924 * pci_auto_config_devices() - configure bus devices ready for use
925 *
926 * This works through all devices on a bus by scanning the driver model
927 * data structures (normally these have been set up by pci_bind_bus_devices()
928 * earlier).
929 *
930 * Space is allocated for each PCI base address register (BAR) so that the
931 * devices are mapped into memory and I/O space ready for use.
932 *
933 * @bus: Bus containing devices to bind
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100934 * Return: 0 if OK, -ve on error
Simon Glassff3e0772015-03-05 12:25:25 -0700935 */
936int pci_auto_config_devices(struct udevice *bus);
937
938/**
Simon Glassf3f1fae2015-11-29 13:17:48 -0700939 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
Simon Glassff3e0772015-03-05 12:25:25 -0700940 *
941 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
942 * @devp: Returns the device for this address, if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100943 * Return: 0 if OK, -ENODEV if not found
Simon Glassff3e0772015-03-05 12:25:25 -0700944 */
Simon Glassf3f1fae2015-11-29 13:17:48 -0700945int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
Simon Glassff3e0772015-03-05 12:25:25 -0700946
947/**
948 * pci_bus_find_devfn() - Find a device on a bus
949 *
950 * @find_devfn: PCI device address (device and function only)
951 * @devp: Returns the device for this address, if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100952 * Return: 0 if OK, -ENODEV if not found
Simon Glassff3e0772015-03-05 12:25:25 -0700953 */
Simon Glassc4e72c42020-01-27 08:49:37 -0700954int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
Simon Glassff3e0772015-03-05 12:25:25 -0700955 struct udevice **devp);
956
957/**
Simon Glass76c3fbc2015-08-10 07:05:04 -0600958 * pci_find_first_device() - return the first available PCI device
959 *
Michal Suchanek1fcfadc2022-09-27 23:25:24 +0200960 * This function and pci_find_next_device() allow iteration through all
Simon Glass76c3fbc2015-08-10 07:05:04 -0600961 * available PCI devices on all buses. Assuming there are any, this will
962 * return the first one.
963 *
964 * @devp: Set to the first available device, or NULL if no more are left
965 * or we got an error
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100966 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
Simon Glass76c3fbc2015-08-10 07:05:04 -0600967 */
968int pci_find_first_device(struct udevice **devp);
969
970/**
971 * pci_find_next_device() - return the next available PCI device
972 *
973 * Finds the next available PCI device after the one supplied, or sets @devp
974 * to NULL if there are no more.
975 *
976 * @devp: On entry, the last device returned. Set to the next available
977 * device, or NULL if no more are left or we got an error
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100978 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
Simon Glass76c3fbc2015-08-10 07:05:04 -0600979 */
980int pci_find_next_device(struct udevice **devp);
981
982/**
Simon Glassff3e0772015-03-05 12:25:25 -0700983 * pci_get_ff() - Returns a mask for the given access size
984 *
985 * @size: Access size
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100986 * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
Simon Glassff3e0772015-03-05 12:25:25 -0700987 * PCI_SIZE_32
988 */
989int pci_get_ff(enum pci_size_t size);
990
991/**
992 * pci_bus_find_devices () - Find devices on a bus
993 *
994 * @bus: Bus to search
995 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
996 * @indexp: Pointer to device index to find. To find the first matching
997 * device, pass 0; to find the second, pass 1, etc. This
998 * parameter is decremented for each non-matching device so
999 * can be called repeatedly.
1000 * @devp: Returns matching device if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001001 * Return: 0 if found, -ENODEV if not
Simon Glassff3e0772015-03-05 12:25:25 -07001002 */
Simon Glasse58f3a72021-06-27 17:50:56 -06001003int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
Simon Glassff3e0772015-03-05 12:25:25 -07001004 int *indexp, struct udevice **devp);
1005
1006/**
1007 * pci_find_device_id() - Find a device on any bus
1008 *
1009 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1010 * @index: Index number of device to find, 0 for the first match, 1 for
1011 * the second, etc.
1012 * @devp: Returns matching device if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001013 * Return: 0 if found, -ENODEV if not
Simon Glassff3e0772015-03-05 12:25:25 -07001014 */
Simon Glasse58f3a72021-06-27 17:50:56 -06001015int pci_find_device_id(const struct pci_device_id *ids, int index,
Simon Glassff3e0772015-03-05 12:25:25 -07001016 struct udevice **devp);
1017
1018/**
1019 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1020 *
1021 * This probes the given bus which causes it to be scanned for devices. The
1022 * devices will be bound but not probed.
1023 *
1024 * @hose specifies the PCI hose that will be used for the scan. This is
1025 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1026 * in @bdf, and is a subordinate bus reachable from @hose.
1027 *
1028 * @hose: PCI hose to scan
1029 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001030 * Return: 0 if OK, -ve on error
Simon Glassff3e0772015-03-05 12:25:25 -07001031 */
Simon Glass5e23b8b2015-11-29 13:17:49 -07001032int dm_pci_hose_probe_bus(struct udevice *bus);
Simon Glassff3e0772015-03-05 12:25:25 -07001033
1034/**
1035 * pci_bus_read_config() - Read a configuration value from a device
1036 *
1037 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1038 * it do the right thing. It would be good to have that function also.
1039 *
1040 * @bus: Bus to read from
1041 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001042 * @offset: Register offset to read
Simon Glassff3e0772015-03-05 12:25:25 -07001043 * @valuep: Place to put the returned value
1044 * @size: Access size
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001045 * Return: 0 if OK, -ve on error
Simon Glassff3e0772015-03-05 12:25:25 -07001046 */
Simon Glass194fca92020-01-27 08:49:38 -07001047int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
Simon Glassff3e0772015-03-05 12:25:25 -07001048 unsigned long *valuep, enum pci_size_t size);
1049
1050/**
1051 * pci_bus_write_config() - Write a configuration value to a device
1052 *
1053 * @bus: Bus to write from
1054 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001055 * @offset: Register offset to write
Simon Glassff3e0772015-03-05 12:25:25 -07001056 * @value: Value to write
1057 * @size: Access size
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001058 * Return: 0 if OK, -ve on error
Simon Glassff3e0772015-03-05 12:25:25 -07001059 */
1060int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1061 unsigned long value, enum pci_size_t size);
1062
Simon Glass66afb4e2015-08-10 07:05:03 -06001063/**
Simon Glass319dba12016-03-06 19:27:52 -07001064 * pci_bus_clrset_config32() - Update a configuration value for a device
1065 *
1066 * The register at @offset is updated to (oldvalue & ~clr) | set.
1067 *
1068 * @bus: Bus to access
1069 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1070 * @offset: Register offset to update
1071 * @clr: Bits to clear
1072 * @set: Bits to set
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001073 * Return: 0 if OK, -ve on error
Simon Glass319dba12016-03-06 19:27:52 -07001074 */
1075int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1076 u32 clr, u32 set);
1077
1078/**
Simon Glass66afb4e2015-08-10 07:05:03 -06001079 * Driver model PCI config access functions. Use these in preference to others
1080 * when you have a valid device
1081 */
Simon Glass194fca92020-01-27 08:49:38 -07001082int dm_pci_read_config(const struct udevice *dev, int offset,
1083 unsigned long *valuep, enum pci_size_t size);
Simon Glass66afb4e2015-08-10 07:05:03 -06001084
Simon Glass194fca92020-01-27 08:49:38 -07001085int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
1086int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
1087int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
Simon Glass66afb4e2015-08-10 07:05:03 -06001088
1089int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1090 enum pci_size_t size);
1091
1092int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1093int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1094int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1095
Simon Glass319dba12016-03-06 19:27:52 -07001096/**
1097 * These permit convenient read/modify/write on PCI configuration. The
1098 * register is updated to (oldvalue & ~clr) | set.
1099 */
1100int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1101int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1102int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1103
Simon Glassff3e0772015-03-05 12:25:25 -07001104/*
1105 * The following functions provide access to the above without needing the
1106 * size parameter. We are trying to encourage the use of the 8/16/32-style
1107 * functions, rather than byte/word/dword. But both are supported.
1108 */
1109int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
Bin Meng308143e2016-02-02 05:58:07 -08001110int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1111int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1112int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1113int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1114int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
Simon Glassff3e0772015-03-05 12:25:25 -07001115
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001116/**
1117 * pci_generic_mmap_write_config() - Generic helper for writing to
1118 * memory-mapped PCI configuration space.
1119 * @bus: Pointer to the PCI bus
1120 * @addr_f: Callback for calculating the config space address
1121 * @bdf: Identifies the PCI device to access
1122 * @offset: The offset into the device's configuration space
1123 * @value: The value to write
1124 * @size: Indicates the size of access to perform
1125 *
1126 * Write the value @value of size @size from offset @offset within the
1127 * configuration space of the device identified by the bus, device & function
1128 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1129 * responsible for calculating the CPU address of the respective configuration
1130 * space offset.
1131 *
1132 * Return: 0 on success, else -EINVAL
1133 */
1134int pci_generic_mmap_write_config(
Simon Glassc4e72c42020-01-27 08:49:37 -07001135 const struct udevice *bus,
1136 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1137 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001138 pci_dev_t bdf,
1139 uint offset,
1140 ulong value,
1141 enum pci_size_t size);
1142
1143/**
1144 * pci_generic_mmap_read_config() - Generic helper for reading from
1145 * memory-mapped PCI configuration space.
1146 * @bus: Pointer to the PCI bus
1147 * @addr_f: Callback for calculating the config space address
1148 * @bdf: Identifies the PCI device to access
1149 * @offset: The offset into the device's configuration space
1150 * @valuep: A pointer at which to store the read value
1151 * @size: Indicates the size of access to perform
1152 *
1153 * Read a value of size @size from offset @offset within the configuration
1154 * space of the device identified by the bus, device & function numbers in @bdf
1155 * on the PCI bus @bus. The callback function @addr_f is responsible for
1156 * calculating the CPU address of the respective configuration space offset.
1157 *
1158 * Return: 0 on success, else -EINVAL
1159 */
1160int pci_generic_mmap_read_config(
Simon Glassc4e72c42020-01-27 08:49:37 -07001161 const struct udevice *bus,
1162 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1163 void **addrp),
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001164 pci_dev_t bdf,
1165 uint offset,
1166 ulong *valuep,
1167 enum pci_size_t size);
1168
Suneel Garapatib8852dc2019-10-19 16:07:20 -07001169#if defined(CONFIG_PCI_SRIOV)
1170/**
1171 * pci_sriov_init() - Scan Virtual Function devices
1172 *
1173 * @pdev: Physical Function udevice handle
1174 * @vf_en: Number of Virtual Function devices to enable
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001175 * Return: 0 on success, -ve on error
Suneel Garapatib8852dc2019-10-19 16:07:20 -07001176 */
1177int pci_sriov_init(struct udevice *pdev, int vf_en);
1178
1179/**
1180 * pci_sriov_get_totalvfs() - Get total available Virtual Function devices
1181 *
1182 * @pdev: Physical Function udevice handle
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001183 * Return: count on success, -ve on error
Suneel Garapatib8852dc2019-10-19 16:07:20 -07001184 */
1185int pci_sriov_get_totalvfs(struct udevice *pdev);
1186#endif
1187
Simon Glass3ba5f742015-11-26 19:51:30 -07001188#ifdef CONFIG_DM_PCI_COMPAT
Simon Glassff3e0772015-03-05 12:25:25 -07001189/* Compatibility with old naming */
1190static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1191 u32 value)
1192{
1193 return pci_write_config32(pcidev, offset, value);
1194}
1195
Simon Glassff3e0772015-03-05 12:25:25 -07001196/* Compatibility with old naming */
1197static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1198 u16 value)
1199{
1200 return pci_write_config16(pcidev, offset, value);
1201}
1202
Simon Glassff3e0772015-03-05 12:25:25 -07001203/* Compatibility with old naming */
1204static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1205 u8 value)
1206{
1207 return pci_write_config8(pcidev, offset, value);
1208}
1209
Simon Glassff3e0772015-03-05 12:25:25 -07001210/* Compatibility with old naming */
1211static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1212 u32 *valuep)
1213{
1214 return pci_read_config32(pcidev, offset, valuep);
1215}
1216
Simon Glassff3e0772015-03-05 12:25:25 -07001217/* Compatibility with old naming */
1218static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1219 u16 *valuep)
1220{
1221 return pci_read_config16(pcidev, offset, valuep);
1222}
1223
Simon Glassff3e0772015-03-05 12:25:25 -07001224/* Compatibility with old naming */
1225static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1226 u8 *valuep)
1227{
1228 return pci_read_config8(pcidev, offset, valuep);
1229}
Simon Glass3ba5f742015-11-26 19:51:30 -07001230#endif /* CONFIG_DM_PCI_COMPAT */
1231
1232/**
1233 * dm_pciauto_config_device() - configure a device ready for use
1234 *
1235 * Space is allocated for each PCI base address register (BAR) so that the
1236 * devices are mapped into memory and I/O space ready for use.
1237 *
1238 * @dev: Device to configure
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001239 * Return: 0 if OK, -ve on error
Simon Glass3ba5f742015-11-26 19:51:30 -07001240 */
1241int dm_pciauto_config_device(struct udevice *dev);
1242
Simon Glass36d0d3b2015-03-05 12:25:28 -07001243/**
Simon Glass9289db62015-11-19 20:26:59 -07001244 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1245 *
1246 * Some PCI buses must always perform 32-bit reads. The data must then be
1247 * shifted and masked to reflect the required access size and offset. This
1248 * function performs this transformation.
1249 *
1250 * @value: Value to transform (32-bit value read from @offset & ~3)
1251 * @offset: Register offset that was read
1252 * @size: Required size of the result
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001253 * Return: the value that would have been obtained if the read had been
Simon Glass9289db62015-11-19 20:26:59 -07001254 * performed at the given offset with the correct size
1255 */
1256ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1257
1258/**
1259 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1260 *
1261 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1262 * write the old 32-bit data must be read, updated with the required new data
1263 * and written back as a 32-bit value. This function performs the
1264 * transformation from the old value to the new value.
1265 *
1266 * @value: Value to transform (32-bit value read from @offset & ~3)
1267 * @offset: Register offset that should be written
1268 * @size: Required size of the write
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001269 * Return: the value that should be written as a 32-bit access to @offset & ~3.
Simon Glass9289db62015-11-19 20:26:59 -07001270 */
1271ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1272 enum pci_size_t size);
1273
1274/**
Simon Glass9f60fb02015-11-19 20:27:00 -07001275 * pci_get_controller() - obtain the controller to use for a bus
1276 *
1277 * @dev: Device to check
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001278 * Return: pointer to the controller device for this bus
Simon Glass9f60fb02015-11-19 20:27:00 -07001279 */
1280struct udevice *pci_get_controller(struct udevice *dev);
1281
1282/**
Simon Glassf9260332015-11-19 20:27:01 -07001283 * pci_get_regions() - obtain pointers to all the region types
1284 *
1285 * @dev: Device to check
1286 * @iop: Returns a pointer to the I/O region, or NULL if none
1287 * @memp: Returns a pointer to the memory region, or NULL if none
1288 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001289 * Return: the number of non-NULL regions returned, normally 3
Simon Glassf9260332015-11-19 20:27:01 -07001290 */
1291int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1292 struct pci_region **memp, struct pci_region **prefp);
Rayagonda Kokatanur143eb5b2020-05-12 13:29:49 +05301293int
1294pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
Simon Glassf9260332015-11-19 20:27:01 -07001295/**
Simon Glass9d731c82016-01-18 20:19:15 -07001296 * dm_pci_write_bar32() - Write the address of a BAR
1297 *
1298 * This writes a raw address to a bar
1299 *
1300 * @dev: PCI device to update
1301 * @barnum: BAR number (0-5)
1302 * @addr: BAR address
1303 */
1304void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1305
1306/**
Simon Glassbab17cf2015-11-29 13:17:53 -07001307 * dm_pci_read_bar32() - read a base address register from a device
1308 *
1309 * @dev: Device to check
1310 * @barnum: Bar number to read (numbered from 0)
1311 * @return: value of BAR
1312 */
Simon Glass194fca92020-01-27 08:49:38 -07001313u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
Simon Glassbab17cf2015-11-29 13:17:53 -07001314
1315/**
Andrew Scull398dc362022-04-21 16:11:08 +00001316 * dm_pci_bus_to_phys() - convert a PCI bus address range to a physical address
Simon Glass21d1fe72015-11-29 13:18:03 -07001317 *
1318 * @dev: Device containing the PCI address
1319 * @addr: PCI address to convert
Andrew Scull398dc362022-04-21 16:11:08 +00001320 * @len: Length of the address range
Andrew Scull7739d932022-04-21 16:11:11 +00001321 * @mask: Mask to match flags for the region type
Simon Glass21d1fe72015-11-29 13:18:03 -07001322 * @flags: Flags for the region type (PCI_REGION_...)
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001323 * Return: physical address corresponding to that PCI bus address
Simon Glass21d1fe72015-11-29 13:18:03 -07001324 */
Andrew Scull398dc362022-04-21 16:11:08 +00001325phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, size_t len,
Andrew Scull7739d932022-04-21 16:11:11 +00001326 unsigned long mask, unsigned long flags);
Simon Glass21d1fe72015-11-29 13:18:03 -07001327
1328/**
1329 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1330 *
1331 * @dev: Device containing the bus address
1332 * @addr: Physical address to convert
Andrew Scull398dc362022-04-21 16:11:08 +00001333 * @len: Length of the address range
Andrew Scull7739d932022-04-21 16:11:11 +00001334 * @mask: Mask to match flags for the region type
Simon Glass21d1fe72015-11-29 13:18:03 -07001335 * @flags: Flags for the region type (PCI_REGION_...)
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001336 * Return: PCI bus address corresponding to that physical address
Simon Glass21d1fe72015-11-29 13:18:03 -07001337 */
Andrew Scull398dc362022-04-21 16:11:08 +00001338pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len,
Andrew Scull7739d932022-04-21 16:11:11 +00001339 unsigned long mask, unsigned long flags);
Simon Glass21d1fe72015-11-29 13:18:03 -07001340
1341/**
1342 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1343 *
1344 * Looks up a base address register and finds the physical memory address
Alex Marginean2204bc12019-06-07 11:24:22 +03001345 * that corresponds to it.
1346 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
1347 * type 1 functions.
Alex Marginean0b143d82019-06-07 11:24:23 +03001348 * Can also be used on type 0 functions that support Enhanced Allocation for
1349 * 32b/64b BARs. Note that duplicate BEI entries are not supported.
Simon Glass21d1fe72015-11-29 13:18:03 -07001350 *
1351 * @dev: Device to check
Alex Marginean2204bc12019-06-07 11:24:22 +03001352 * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
Andrew Scull12507a22022-04-21 16:11:10 +00001353 * @offset: Offset from the base to map
1354 * @len: Length to map
Andrew Scull2635e3b2022-04-21 16:11:13 +00001355 * @mask: Mask to match flags for the region type
Simon Glass21d1fe72015-11-29 13:18:03 -07001356 * @flags: Flags for the region type (PCI_REGION_...)
Alex Marginean2204bc12019-06-07 11:24:22 +03001357 * @return: pointer to the virtual address to use or 0 on error
Simon Glass21d1fe72015-11-29 13:18:03 -07001358 */
Andrew Scull12507a22022-04-21 16:11:10 +00001359void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
Andrew Scull2635e3b2022-04-21 16:11:13 +00001360 unsigned long mask, unsigned long flags);
Simon Glass21d1fe72015-11-29 13:18:03 -07001361
Bin Mengdac01fd2018-08-03 01:14:52 -07001362/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001363 * dm_pci_find_next_capability() - find a capability starting from an offset
1364 *
1365 * Tell if a device supports a given PCI capability. Returns the
1366 * address of the requested capability structure within the device's
1367 * PCI configuration space or 0 in case the device does not support it.
1368 *
1369 * Possible values for @cap:
1370 *
1371 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1372 * %PCI_CAP_ID_PCIX PCI-X
1373 * %PCI_CAP_ID_EXP PCI Express
1374 * %PCI_CAP_ID_MSIX MSI-X
1375 *
1376 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1377 *
1378 * @dev: PCI device to query
1379 * @start: offset to start from
1380 * @cap: capability code
1381 * @return: capability address or 0 if not supported
1382 */
1383int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1384
1385/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001386 * dm_pci_find_capability() - find a capability
1387 *
1388 * Tell if a device supports a given PCI capability. Returns the
1389 * address of the requested capability structure within the device's
1390 * PCI configuration space or 0 in case the device does not support it.
1391 *
1392 * Possible values for @cap:
1393 *
1394 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1395 * %PCI_CAP_ID_PCIX PCI-X
1396 * %PCI_CAP_ID_EXP PCI Express
1397 * %PCI_CAP_ID_MSIX MSI-X
1398 *
1399 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1400 *
1401 * @dev: PCI device to query
1402 * @cap: capability code
1403 * @return: capability address or 0 if not supported
1404 */
1405int dm_pci_find_capability(struct udevice *dev, int cap);
1406
1407/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001408 * dm_pci_find_next_ext_capability() - find an extended capability
1409 * starting from an offset
1410 *
1411 * Tell if a device supports a given PCI express extended capability.
1412 * Returns the address of the requested extended capability structure
1413 * within the device's PCI configuration space or 0 in case the device
1414 * does not support it.
1415 *
1416 * Possible values for @cap:
1417 *
1418 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1419 * %PCI_EXT_CAP_ID_VC Virtual Channel
1420 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1421 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1422 *
1423 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1424 *
1425 * @dev: PCI device to query
1426 * @start: offset to start from
1427 * @cap: extended capability code
1428 * @return: extended capability address or 0 if not supported
1429 */
1430int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1431
1432/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001433 * dm_pci_find_ext_capability() - find an extended capability
1434 *
1435 * Tell if a device supports a given PCI express extended capability.
1436 * Returns the address of the requested extended capability structure
1437 * within the device's PCI configuration space or 0 in case the device
1438 * does not support it.
1439 *
1440 * Possible values for @cap:
1441 *
1442 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1443 * %PCI_EXT_CAP_ID_VC Virtual Channel
1444 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1445 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1446 *
1447 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1448 *
1449 * @dev: PCI device to query
1450 * @cap: extended capability code
1451 * @return: extended capability address or 0 if not supported
1452 */
1453int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1454
Alex Margineanb8e1f822019-06-07 11:24:25 +03001455/**
1456 * dm_pci_flr() - Perform FLR if the device suppoorts it
1457 *
1458 * @dev: PCI device to reset
1459 * @return: 0 if OK, -ENOENT if FLR is not supported by dev
1460 */
1461int dm_pci_flr(struct udevice *dev);
1462
Simon Glass21d1fe72015-11-29 13:18:03 -07001463#define dm_pci_virt_to_bus(dev, addr, flags) \
Andrew Scull7739d932022-04-21 16:11:11 +00001464 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), 0, PCI_REGION_TYPE, (flags))
Andrew Sculla822d1d2022-04-21 16:11:12 +00001465#define dm_pci_bus_to_virt(dev, addr, len, mask, flags, map_flags) \
1466({ \
1467 size_t _len = (len); \
1468 phys_addr_t phys_addr = dm_pci_bus_to_phys((dev), (addr), _len, \
1469 (mask), (flags)); \
1470 map_physmem(phys_addr, _len, (map_flags)); \
1471})
Simon Glass21d1fe72015-11-29 13:18:03 -07001472
1473#define dm_pci_phys_to_mem(dev, addr) \
Andrew Scull7739d932022-04-21 16:11:11 +00001474 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
Simon Glass21d1fe72015-11-29 13:18:03 -07001475#define dm_pci_mem_to_phys(dev, addr) \
Andrew Scull7739d932022-04-21 16:11:11 +00001476 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
Simon Glass21d1fe72015-11-29 13:18:03 -07001477#define dm_pci_phys_to_io(dev, addr) \
Andrew Scull7739d932022-04-21 16:11:11 +00001478 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001479#define dm_pci_io_to_phys(dev, addr) \
Andrew Scull7739d932022-04-21 16:11:11 +00001480 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001481
1482#define dm_pci_virt_to_mem(dev, addr) \
1483 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1484#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
Andrew Sculla822d1d2022-04-21 16:11:12 +00001485 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1486 PCI_REGION_MEM, (map_flags))
Simon Glass21d1fe72015-11-29 13:18:03 -07001487#define dm_pci_virt_to_io(dev, addr) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001488 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001489#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
Andrew Sculla822d1d2022-04-21 16:11:12 +00001490 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1491 PCI_REGION_IO, (map_flags))
Simon Glass21d1fe72015-11-29 13:18:03 -07001492
1493/**
Simon Glass5c0bf642015-11-29 13:17:50 -07001494 * dm_pci_find_device() - find a device by vendor/device ID
1495 *
1496 * @vendor: Vendor ID
1497 * @device: Device ID
1498 * @index: 0 to find the first match, 1 for second, etc.
1499 * @devp: Returns pointer to the device, if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001500 * Return: 0 if found, -ve on error
Simon Glass5c0bf642015-11-29 13:17:50 -07001501 */
1502int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1503 struct udevice **devp);
1504
1505/**
Simon Glassa0eb8352015-11-29 13:17:52 -07001506 * dm_pci_find_class() - find a device by class
1507 *
1508 * @find_class: 3-byte (24-bit) class value to find
1509 * @index: 0 to find the first match, 1 for second, etc.
1510 * @devp: Returns pointer to the device, if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001511 * Return: 0 if found, -ve on error
Simon Glassa0eb8352015-11-29 13:17:52 -07001512 */
1513int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1514
1515/**
Simon Glass6498fda2019-09-21 14:32:41 -06001516 * struct pci_emul_uc_priv - holds info about an emulator device
1517 *
1518 * There is always at most one emulator per client
1519 *
1520 * @client: Client device if any, else NULL
1521 */
1522struct pci_emul_uc_priv {
1523 struct udevice *client;
1524};
1525
1526/**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001527 * struct dm_pci_emul_ops - PCI device emulator operations
1528 */
1529struct dm_pci_emul_ops {
1530 /**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001531 * read_config() - Read a PCI configuration value
1532 *
1533 * @dev: Emulated device to read from
1534 * @offset: Byte offset within the device's configuration space
1535 * @valuep: Place to put the returned value
1536 * @size: Access size
1537 * @return 0 if OK, -ve on error
1538 */
Simon Glassc4e72c42020-01-27 08:49:37 -07001539 int (*read_config)(const struct udevice *dev, uint offset,
1540 ulong *valuep, enum pci_size_t size);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001541 /**
1542 * write_config() - Write a PCI configuration value
1543 *
1544 * @dev: Emulated device to write to
1545 * @offset: Byte offset within the device's configuration space
1546 * @value: Value to write
1547 * @size: Access size
1548 * @return 0 if OK, -ve on error
1549 */
1550 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1551 enum pci_size_t size);
1552 /**
1553 * read_io() - Read a PCI I/O value
1554 *
1555 * @dev: Emulated device to read from
1556 * @addr: I/O address to read
1557 * @valuep: Place to put the returned value
1558 * @size: Access size
1559 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1560 * other -ve value on error
1561 */
1562 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1563 enum pci_size_t size);
1564 /**
1565 * write_io() - Write a PCI I/O value
1566 *
1567 * @dev: Emulated device to write from
1568 * @addr: I/O address to write
1569 * @value: Value to write
1570 * @size: Access size
1571 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1572 * other -ve value on error
1573 */
1574 int (*write_io)(struct udevice *dev, unsigned int addr,
1575 ulong value, enum pci_size_t size);
1576 /**
1577 * map_physmem() - Map a device into sandbox memory
1578 *
1579 * @dev: Emulated device to map
1580 * @addr: Memory address, normally corresponding to a PCI BAR.
1581 * The device should have been configured to have a BAR
1582 * at this address.
1583 * @lenp: On entry, the size of the area to map, On exit it is
1584 * updated to the size actually mapped, which may be less
1585 * if the device has less space
1586 * @ptrp: Returns a pointer to the mapped address. The device's
1587 * space can be accessed as @lenp bytes starting here
1588 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1589 * other -ve value on error
1590 */
1591 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1592 unsigned long *lenp, void **ptrp);
1593 /**
1594 * unmap_physmem() - undo a memory mapping
1595 *
1596 * This must be called after map_physmem() to undo the mapping.
1597 * Some devices can use this to check what has been written into
1598 * their mapped memory and perform an operations they require on it.
1599 * In this way, map/unmap can be used as a sort of handshake between
1600 * the emulated device and its users.
1601 *
1602 * @dev: Emuated device to unmap
1603 * @vaddr: Mapped memory address, as passed to map_physmem()
1604 * @len: Size of area mapped, as returned by map_physmem()
1605 * @return 0 if OK, -ve on error
1606 */
1607 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1608 unsigned long len);
1609};
1610
1611/* Get access to a PCI device emulator's operations */
1612#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1613
1614/**
1615 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1616 *
1617 * Searches for a suitable emulator for the given PCI bus device
1618 *
1619 * @bus: PCI bus to search
1620 * @find_devfn: PCI device and function address (PCI_DEVFN())
Bin Meng43459982018-08-03 01:14:45 -07001621 * @containerp: Returns container device if found
Simon Glass36d0d3b2015-03-05 12:25:28 -07001622 * @emulp: Returns emulated device if found
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001623 * Return: 0 if found, -ENODEV if not found
Simon Glass36d0d3b2015-03-05 12:25:28 -07001624 */
Simon Glassc4e72c42020-01-27 08:49:37 -07001625int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
Bin Meng43459982018-08-03 01:14:45 -07001626 struct udevice **containerp, struct udevice **emulp);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001627
Stefan Roeseb5214202019-01-25 11:52:42 +01001628/**
Simon Glass6498fda2019-09-21 14:32:41 -06001629 * sandbox_pci_get_client() - Find the client for an emulation device
1630 *
1631 * @emul: Emulation device to check
1632 * @devp: Returns the client device emulated by this device
Heinrich Schuchardt185f8122022-01-19 18:05:50 +01001633 * Return: 0 if OK, -ENOENT if the device has no client yet
Simon Glass6498fda2019-09-21 14:32:41 -06001634 */
1635int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
1636
Tim Harveycecd0132021-04-16 14:53:47 -07001637/**
1638 * board_pci_fixup_dev() - Board callback for PCI device fixups
1639 *
1640 * @bus: PCI bus
1641 * @dev: PCI device
1642 */
1643extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
1644
Simon Glassaba92962015-07-06 16:47:44 -06001645/**
1646 * PCI_DEVICE - macro used to describe a specific pci device
1647 * @vend: the 16 bit PCI Vendor ID
1648 * @dev: the 16 bit PCI Device ID
1649 *
1650 * This macro is used to create a struct pci_device_id that matches a
1651 * specific device. The subvendor and subdevice fields will be set to
1652 * PCI_ANY_ID.
1653 */
1654#define PCI_DEVICE(vend, dev) \
1655 .vendor = (vend), .device = (dev), \
1656 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1657
1658/**
1659 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1660 * @vend: the 16 bit PCI Vendor ID
1661 * @dev: the 16 bit PCI Device ID
1662 * @subvend: the 16 bit PCI Subvendor ID
1663 * @subdev: the 16 bit PCI Subdevice ID
1664 *
1665 * This macro is used to create a struct pci_device_id that matches a
1666 * specific device with subsystem information.
1667 */
1668#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1669 .vendor = (vend), .device = (dev), \
1670 .subvendor = (subvend), .subdevice = (subdev)
1671
1672/**
1673 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1674 * @dev_class: the class, subclass, prog-if triple for this device
1675 * @dev_class_mask: the class mask for this device
1676 *
1677 * This macro is used to create a struct pci_device_id that matches a
1678 * specific PCI class. The vendor, device, subvendor, and subdevice
1679 * fields will be set to PCI_ANY_ID.
1680 */
1681#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1682 .class = (dev_class), .class_mask = (dev_class_mask), \
1683 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1684 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1685
1686/**
1687 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1688 * @vend: the vendor name
1689 * @dev: the 16 bit PCI Device ID
1690 *
1691 * This macro is used to create a struct pci_device_id that matches a
1692 * specific PCI device. The subvendor, and subdevice fields will be set
1693 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1694 * private data.
1695 */
1696
1697#define PCI_VDEVICE(vend, dev) \
1698 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1699 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1700
1701/**
1702 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1703 * @driver: Driver to use
1704 * @match: List of match records for this driver, terminated by {}
1705 */
1706struct pci_driver_entry {
1707 struct driver *driver;
1708 const struct pci_device_id *match;
1709};
1710
1711#define U_BOOT_PCI_DEVICE(__name, __match) \
1712 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1713 .driver = llsym(struct driver, __name, driver), \
1714 .match = __match, \
1715 }
Simon Glassff3e0772015-03-05 12:25:25 -07001716
Paul Burtonfa5cec02013-11-08 11:18:47 +00001717#endif /* __ASSEMBLY__ */
1718#endif /* _PCI_H */