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Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +09001#ifndef __CONFIG_H
2#define __CONFIG_H
3
4#undef DEBUG
5
6#define CONFIG_SH 1
7#define CONFIG_SH4 1
8#define CONFIG_CPU_SH7751 1
9#define CONFIG_CPU_SH_TYPE_R 1
10#define CONFIG_R2DPLUS 1
11#define __LITTLE_ENDIAN__ 1
12
13/*
14 * Command line configuration.
15 */
16#include <config_cmd_default.h>
17
18#define CONFIG_CMD_DFL
19#define CONFIG_CMD_CACHE
20#define CONFIG_CMD_FLASH
21#define CONFIG_CMD_PCI
22#define CONFIG_CMD_NET
23#define CONFIG_CMD_PING
24#define CONFIG_CMD_IDE
25#define CONFIG_CMD_EXT2
26#define CONFIG_DOS_PARTITION
27
28/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020029#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090030#define CONFIG_BAUDRATE 115200
31#define CONFIG_CONS_SCIF1 1
32#define BOARD_LATE_INIT 1
33
34#define CONFIG_BOOTDELAY -1
35#define CONFIG_BOOTARGS "console=ttySC0,115200"
36#define CONFIG_ENV_OVERWRITE 1
37
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090038/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
40#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_LONGHELP
43#define CONFIG_SYS_PROMPT "=> "
44#define CONFIG_SYS_CBSIZE 256
45#define CONFIG_SYS_PBSIZE 256
46#define CONFIG_SYS_MAXARGS 16
47#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090048/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
52#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090053
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090055/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
57#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090058/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090060/* size in bytes reserved for initial data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_GBL_DATA_SIZE (256)
62#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090063
64/*
Nobuhiro Iwamatsu873d97a2008-06-17 16:28:05 +090065 * NOR Flash ( Spantion S29GL256P )
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090066 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020068#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_FLASH_BASE (0xA0000000)
70#define CONFIG_SYS_MAX_FLASH_BANKS (1)
71#define CONFIG_SYS_MAX_FLASH_SECT 256
72#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090073
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020074#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020075#define CONFIG_ENV_SECT_SIZE 0x40000
76#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090078
79/*
80 * SuperH Clock setting
81 */
82#define CONFIG_SYS_CLK_FREQ 60000000
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020083#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD8dd29c82009-06-04 12:06:47 +020084#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090086
87/*
88 * IDE support
89 */
90#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_PIO_MODE 1
92#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
93#define CONFIG_SYS_IDE_MAXDEVICE 1
94#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
95#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
96#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
97#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
98#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090099
100/*
101 * SuperH PCI Bridge Configration
102 */
103#define CONFIG_PCI
104#define CONFIG_SH4_PCI
105#define CONFIG_SH7751_PCI
106#define CONFIG_PCI_PNP
107#define CONFIG_PCI_SCAN_SHOW 1
108#define __io
109#define __mem_pci
110
111#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
112#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
113#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
114#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
115#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
116#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
Yoshihiro Shimoda2db0e122009-02-25 16:04:26 +0900117#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
118#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
119#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +0900120
121/*
122 * Network device (RTL8139) support
123 */
124#define CONFIG_NET_MULTI
125#define CONFIG_RTL8139
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +0900126
127#endif /* __CONFIG_H */