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wdenk5b1d7132002-11-03 00:07:02 +00001#ifndef __CONFIG_H
2#define __CONFIG_H
3
4
5/*****************************************************************************
6 *
7 * These settings must match the way _your_ board is set up
8 *
9 *****************************************************************************/
10/* for the AY-Revision which does not use the HRCW */
11#define CFG_DEFAULT_IMMR 0x00010000
12
13/* What is the oscillator's (UX2) frequency in Hz? */
14#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
15
16/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
17 * only the 3 least significant bits are important.
18*/
19#define CFG_SBC_S2 0x04
20
21/* What should MODCK_H be? It is dependent on the oscillator
22 * frequency, MODCK[1-3], and desired CPM and core frequencies.
23 * Some example values (all frequencies are in MHz):
24 *
25 * MODCK_H MODCK[1-3] Osc CPM Core
26 * 0x2 0x2 33 133 133
27 * 0x2 0x4 33 133 200
28 * 0x5 0x5 66 133 133
29 * 0x5 0x7 66 133 200
30 */
31#define CFG_SBC_MODCK_H 0x06
32
33#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */
34#undef CFG_SBC_BOOT_LOW
35
36/* What should the base address of the main FLASH be and how big is
37 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
38 * The main FLASH is whichever is connected to *CS0. U-Boot expects
39 * this to be the SIMM.
40 */
41#define CFG_FLASH0_BASE 0x80000000
42#define CFG_FLASH0_SIZE 16
43
44/* What should the base address of the secondary FLASH be and how big
45 * is it (in Mbytes)? The secondary FLASH is whichever is connected
46 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
47 * want it enabled, don't define these constants.
48 */
49#define CFG_FLASH1_BASE 0
50#define CFG_FLASH1_SIZE 0
51#undef CFG_FLASH1_BASE
52#undef CFG_FLASH1_SIZE
53
54/* What should be the base address of SDRAM DIMM and how big is
55 * it (in Mbytes)?
56*/
57#define CFG_SDRAM0_BASE 0x00000000
58#define CFG_SDRAM0_SIZE 64
59
60/* What should be the base address of SDRAM DIMM and how big is
61 * it (in Mbytes)?
62*/
63#define CFG_SDRAM1_BASE 0x04000000
64#define CFG_SDRAM1_SIZE 32
65
66/* What should be the base address of the LEDs and switch S0?
67 * If you don't want them enabled, don't define this.
68 */
69#define CFG_LED_BASE 0x00000000
70
71/*
72 * select serial console configuration
73 *
74 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
75 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
76 * for SCC).
77 *
78 * if CONFIG_CONS_NONE is defined, then the serial console routines must
79 * defined elsewhere.
80 */
81#define CONFIG_CONS_ON_SMC /* define if console on SMC */
82#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
83#undef CONFIG_CONS_NONE /* define if console on neither */
84#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
85
86/*
87 * select ethernet configuration
88 *
89 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
90 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
91 * for FCC)
92 *
93 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050094 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk5b1d7132002-11-03 00:07:02 +000095 */
96#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
97#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
98#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
99#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
100
101#if ( CONFIG_ETHER_INDEX == 3 )
102
103/*
104 * - Rx-CLK is CLK15
105 * - Tx-CLK is CLK16
106 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
107 * - Enable Half Duplex in FSMR
108 */
109# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
110# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
111# define CFG_CPMFCR_RAMTYPE 0
112/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
113# define CFG_FCC_PSMR 0
114
115#else /* CONFIG_ETHER_INDEX */
116# error "on RPX Super ethernet must be FCC3"
117#endif /* CONFIG_ETHER_INDEX */
118
119#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
121#define CFG_I2C_SLAVE 0x7F
122
123
124/* Define this to reserve an entire FLASH sector (256 KB) for
125 * environment variables. Otherwise, the environment will be
126 * put in the same sector as U-Boot, and changing variables
127 * will erase U-Boot temporarily
128 */
129#define CFG_ENV_IN_OWN_SECT
130
131/* Define to allow the user to overwrite serial and ethaddr */
132#define CONFIG_ENV_OVERWRITE
133
134/* What should the console's baud rate be? */
135#define CONFIG_BAUDRATE 115200
136
137/* Ethernet MAC address */
138#define CONFIG_ETHADDR 08:00:22:50:70:63
139
140#define CONFIG_IPADDR 192.168.1.99
141#define CONFIG_SERVERIP 192.168.1.3
142
143/* Set to a positive value to delay for running BOOTCOMMAND */
144#define CONFIG_BOOTDELAY -1
145
146/* undef this to save memory */
147#define CFG_LONGHELP
148
149/* Monitor Command Prompt */
150#define CFG_PROMPT "=> "
151
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500152
153/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500154 * BOOTP options
155 */
156#define CONFIG_BOOTP_BOOTFILESIZE
157#define CONFIG_BOOTP_BOOTPATH
158#define CONFIG_BOOTP_GATEWAY
159#define CONFIG_BOOTP_HOSTNAME
160
161
162/*
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500163 * Command line configuration.
164 */
165#include <config_cmd_default.h>
166
167#define CONFIG_CMD_IMMAP
168#define CONFIG_CMD_ASKENV
169#define CONFIG_CMD_I2C
170#define CONFIG_CMD_REGINFO
171
172#undef CONFIG_CMD_KGDB
173
wdenk5b1d7132002-11-03 00:07:02 +0000174
175/* Where do the internal registers live? */
176#define CFG_IMMR 0xF0000000
177
178/* Where do the on board registers (CS4) live? */
179#define CFG_REGS_BASE 0xFA000000
180
181/*****************************************************************************
182 *
183 * You should not have to modify any of the following settings
184 *
185 *****************************************************************************/
186
187#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
188#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500189#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk5b1d7132002-11-03 00:07:02 +0000190
wdenkc837dcb2004-01-20 23:12:12 +0000191#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk5b1d7132002-11-03 00:07:02 +0000192
wdenk5b1d7132002-11-03 00:07:02 +0000193/*
194 * Miscellaneous configurable options
195 */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500196#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000197# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
198#else
199# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
200#endif
201
202/* Print Buffer Size */
203#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
204
205#define CFG_MAXARGS 8 /* max number of command args */
206
207#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
208
209#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
210#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
211
212#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
213
214#define CFG_LOAD_ADDR 0x100000 /* default load address */
215#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
216
217/* valid baudrates */
218#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
219
220/*
221 * Low Level Configuration Settings
222 * (address mappings, register initial values, etc.)
223 * You should know what you are doing if you make changes here.
224 */
225
226#define CFG_FLASH_BASE CFG_FLASH0_BASE
227#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
228
229/*-----------------------------------------------------------------------
230 * Hard Reset Configuration Words
231 */
232#if defined(CFG_SBC_BOOT_LOW)
233# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
234#else
235# define CFG_SBC_HRCW_BOOT_FLAGS (0)
236#endif /* defined(CFG_SBC_BOOT_LOW) */
237
238/* get the HRCW ISB field from CFG_IMMR */
239#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
wdenk8bde7f72003-06-27 21:31:46 +0000240 ((CFG_IMMR & 0x01000000) >> 7) |\
241 ((CFG_IMMR & 0x00100000) >> 4) )
wdenk5b1d7132002-11-03 00:07:02 +0000242
243#define CFG_HRCW_MASTER (HRCW_BPS11 |\
wdenk8bde7f72003-06-27 21:31:46 +0000244 HRCW_DPPC11 |\
245 CFG_SBC_HRCW_IMMR |\
246 HRCW_MMR00 |\
247 HRCW_LBPC11 |\
248 HRCW_APPC10 |\
249 HRCW_CS10PC00 |\
250 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
251 CFG_SBC_HRCW_BOOT_FLAGS)
wdenk5b1d7132002-11-03 00:07:02 +0000252
253/* no slaves */
254#define CFG_HRCW_SLAVE1 0
255#define CFG_HRCW_SLAVE2 0
256#define CFG_HRCW_SLAVE3 0
257#define CFG_HRCW_SLAVE4 0
258#define CFG_HRCW_SLAVE5 0
259#define CFG_HRCW_SLAVE6 0
260#define CFG_HRCW_SLAVE7 0
261
262/*-----------------------------------------------------------------------
263 * Definitions for initial stack pointer and data area (in DPRAM)
264 */
265#define CFG_INIT_RAM_ADDR CFG_IMMR
266#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
267#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
268#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
269#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
270
271/*-----------------------------------------------------------------------
272 * Start addresses for the final memory configuration
273 * (Set up by the startup code)
274 * Please note that CFG_SDRAM_BASE _must_ start at 0
275 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
276 */
277#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000)
278
279#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
280# define CFG_RAMBOOT
281#endif
282
283#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
284#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
285
286/*
287 * For booting Linux, the board info and command line data
288 * have to be in the first 8 MB of memory, since this is
289 * the maximum mapped by the Linux kernel during initialization.
290 */
291#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
292
293/*-----------------------------------------------------------------------
294 * FLASH and environment organization
295 */
296#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
297#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
298
299#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
300#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
301
302#ifndef CFG_RAMBOOT
303# define CFG_ENV_IS_IN_FLASH 1
304
305# ifdef CFG_ENV_IN_OWN_SECT
306# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
307# define CFG_ENV_SECT_SIZE 0x40000
308# else
309# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
310# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
311# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
312# endif /* CFG_ENV_IN_OWN_SECT */
313#else
314# define CFG_ENV_IS_IN_NVRAM 1
315# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
316# define CFG_ENV_SIZE 0x200
317#endif /* CFG_RAMBOOT */
318
319/*-----------------------------------------------------------------------
320 * Cache Configuration
321 */
322#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
323
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500324#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000325# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
326#endif
327
328/*-----------------------------------------------------------------------
329 * HIDx - Hardware Implementation-dependent Registers 2-11
330 *-----------------------------------------------------------------------
331 * HID0 also contains cache control - initially enable both caches and
332 * invalidate contents, then the final state leaves only the instruction
333 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
334 * but Soft reset does not.
335 *
336 * HID1 has only read-only information - nothing to set.
337 */
338#define CFG_HID0_INIT (/*HID0_ICE |*/\
339 /*HID0_DCE |*/\
340 HID0_ICFI |\
341 HID0_DCI |\
342 HID0_IFEM |\
343 HID0_ABE)
344
345#define CFG_HID0_FINAL (/*HID0_ICE |*/\
346 HID0_IFEM |\
347 HID0_ABE |\
348 HID0_EMCP)
349#define CFG_HID2 0
350
351/*-----------------------------------------------------------------------
352 * RMR - Reset Mode Register
353 *-----------------------------------------------------------------------
354 */
355#define CFG_RMR 0
356
357/*-----------------------------------------------------------------------
358 * BCR - Bus Configuration 4-25
359 *-----------------------------------------------------------------------
360 */
361#define CFG_BCR (BCR_EBM |\
362 BCR_PLDP |\
363 BCR_EAV |\
364 BCR_NPQM0)
365
366/*-----------------------------------------------------------------------
367 * SIUMCR - SIU Module Configuration 4-31
368 *-----------------------------------------------------------------------
369 */
370
371#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
wdenk8bde7f72003-06-27 21:31:46 +0000372 SIUMCR_APPC10 |\
373 SIUMCR_CS10PC01)
wdenk5b1d7132002-11-03 00:07:02 +0000374
375
376/*-----------------------------------------------------------------------
377 * SYPCR - System Protection Control 11-9
378 * SYPCR can only be written once after reset!
379 *-----------------------------------------------------------------------
380 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
381 */
382#define CFG_SYPCR (SYPCR_SWTC |\
wdenk8bde7f72003-06-27 21:31:46 +0000383 SYPCR_BMT |\
384 SYPCR_PBME |\
385 SYPCR_LBME |\
386 SYPCR_SWRI |\
387 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000388
389/*-----------------------------------------------------------------------
390 * TMCNTSC - Time Counter Status and Control 4-40
391 *-----------------------------------------------------------------------
392 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
393 * and enable Time Counter
394 */
395#define CFG_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000396 TMCNTSC_ALR |\
397 TMCNTSC_TCF |\
398 TMCNTSC_TCE)
wdenk5b1d7132002-11-03 00:07:02 +0000399
400/*-----------------------------------------------------------------------
401 * PISCR - Periodic Interrupt Status and Control 4-42
402 *-----------------------------------------------------------------------
403 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
404 * Periodic timer
405 */
406#define CFG_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000407 PISCR_PTF |\
408 PISCR_PTE)
wdenk5b1d7132002-11-03 00:07:02 +0000409
410/*-----------------------------------------------------------------------
411 * SCCR - System Clock Control 9-8
412 *-----------------------------------------------------------------------
413 */
414#define CFG_SCCR (SCCR_DFBRG01)
415
416/*-----------------------------------------------------------------------
417 * RCCR - RISC Controller Configuration 13-7
418 *-----------------------------------------------------------------------
419 */
420#define CFG_RCCR 0
421
422/*
423 * Init Memory Controller:
424 *
425 * Bank Bus Machine PortSz Device
426 * ---- --- ------- ------ ------
427 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
428 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
429 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
430 * 3 unused
431 * 4 60x GPCM 8 bit Board Regs, LEDs, switches
432 * 5 unused
433 * 6 unused
434 * 7 unused
435 * 8 PCMCIA
436 * 9 unused
437 * 10 unused
438 * 11 unused
439*/
440
441/* Bank 0 - FLASH
442 *
443 */
444#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000445 BRx_PS_64 |\
wdenk5b1d7132002-11-03 00:07:02 +0000446 BRx_DECC_NONE |\
wdenk8bde7f72003-06-27 21:31:46 +0000447 BRx_MS_GPCM_P |\
448 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000449
450#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000451 ORxG_CSNT |\
452 ORxG_ACS_DIV1 |\
453 ORxG_SCY_6_CLK |\
454 ORxG_EHTR)
wdenk5b1d7132002-11-03 00:07:02 +0000455
456/* Bank 1 - SDRAM
457 *
458 */
459#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000460 BRx_PS_64 |\
461 BRx_MS_SDRAM_P |\
462 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000463
464#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000465 ORxS_BPD_4 |\
466 ORxS_ROWST_PBI0_A8 |\
467 ORxS_NUMR_12 |\
wdenk5b1d7132002-11-03 00:07:02 +0000468 ORxS_IBID)
469
470#define CFG_PSDMR 0x014DA412
471#define CFG_PSRT 0x79
472
473
474/* Bank 2 - SDRAM
475 *
476 */
477#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000478 BRx_PS_32 |\
479 BRx_MS_SDRAM_L |\
480 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000481
482#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000483 ORxS_BPD_4 |\
484 ORxS_ROWST_PBI0_A9 |\
485 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000486
487#define CFG_LSDMR 0x0169A512
488#define CFG_LSRT 0x79
489
490#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK)
491
492/* Bank 4 - On board registers
493 *
494 */
495#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000496 BRx_PS_8 |\
497 BRx_MS_GPCM_P |\
498 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000499
500#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000501 ORxG_CSNT |\
502 ORxG_ACS_DIV1 |\
503 ORxG_SCY_5_CLK |\
504 ORxG_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000505
506/*
507 * Internal Definitions
508 *
509 * Boot Flags
510 */
511#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
512#define BOOTFLAG_WARM 0x02 /* Software reboot */
513
514#endif /* __CONFIG_H */