blob: 00b78534abdeaabaa6b1d46e301f4c8a5ccdb9cd [file] [log] [blame]
wdenkf12e5682003-07-07 20:07:54 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000053 "echo"
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/TQM860M/uImage\0" \
Martin Krauseda3aad52007-09-26 17:55:56 +020072 "fdt_addr=400C0000\0" \
73 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020074 "ramdisk_addr=40280000\0" \
Martin Krauseda3aad52007-09-26 17:55:56 +020075 "load=tftp 200000 ${u-boot}\0" \
76 "update=protect off 40000000 +${filesize};" \
77 "erase 40000000 +${filesize};" \
78 "cp.b 200000 40000000 ${filesize};" \
79 "protect on 40000000 +${filesize}\0" \
wdenkf12e5682003-07-07 20:07:54 +000080 ""
81#define CONFIG_BOOTCOMMAND "run flash_self"
82
83#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
84#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85
86#undef CONFIG_WATCHDOG /* watchdog disabled */
87
88#define CONFIG_STATUS_LED 1 /* Status LED enabled */
89
90#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
91
Jon Loeliger37d4bb72007-07-09 21:38:02 -050092/*
93 * BOOTP options
94 */
95#define CONFIG_BOOTP_SUBNETMASK
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_BOOTFILESIZE
100
wdenkf12e5682003-07-07 20:07:54 +0000101
102#define CONFIG_MAC_PARTITION
103#define CONFIG_DOS_PARTITION
104
105#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
106
wdenkf12e5682003-07-07 20:07:54 +0000107
Jon Loeliger26946902007-07-04 22:30:50 -0500108/*
109 * Command line configuration.
110 */
111#include <config_cmd_default.h>
112
113#define CONFIG_CMD_ASKENV
114#define CONFIG_CMD_DATE
115#define CONFIG_CMD_DHCP
116#define CONFIG_CMD_ELF
117#define CONFIG_CMD_IDE
118#define CONFIG_CMD_NFS
119#define CONFIG_CMD_SNTP
120
wdenkf12e5682003-07-07 20:07:54 +0000121
122/*
123 * Miscellaneous configurable options
124 */
125#define CFG_LONGHELP /* undef to save memory */
126#define CFG_PROMPT "=> " /* Monitor Command Prompt */
127
Wolfgang Denk2751a952006-10-28 02:29:14 +0200128#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
129#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000130#ifdef CFG_HUSH_PARSER
131#define CFG_PROMPT_HUSH_PS2 "> "
132#endif
133
Jon Loeliger26946902007-07-04 22:30:50 -0500134#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000135#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
136#else
137#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
138#endif
139#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
140#define CFG_MAXARGS 16 /* max number of command args */
141#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
142
143#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
144#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
145
146#define CFG_LOAD_ADDR 0x100000 /* default load address */
147
148#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
149
150#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
151
152/*
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
156 */
157/*-----------------------------------------------------------------------
158 * Internal Memory Mapped Register
159 */
160#define CFG_IMMR 0xFFF00000
161
162/*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM)
164 */
165#define CFG_INIT_RAM_ADDR CFG_IMMR
166#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
167#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
168#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
169#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
170
171/*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CFG_SDRAM_BASE _must_ start at 0
175 */
176#define CFG_SDRAM_BASE 0x00000000
177#define CFG_FLASH_BASE 0x40000000
178#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
179#define CFG_MONITOR_BASE CFG_FLASH_BASE
Martin Krauseda3aad52007-09-26 17:55:56 +0200180#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000181
182/*
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
186 */
187#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188
189/*-----------------------------------------------------------------------
190 * FLASH organization
191 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200192/* use CFI flash driver */
193#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
194#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
195#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
196#define CFG_FLASH_EMPTY_INFO
197#define CFG_FLASH_USE_BUFFER_WRITE 1
198#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
199#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000200
201#define CFG_ENV_IS_IN_FLASH 1
202#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
203#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
Martin Krauseda3aad52007-09-26 17:55:56 +0200204#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000205
206/* Address and size of Redundant Environment Sector */
207#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
208#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
209
Wolfgang Denk67c31032007-09-16 17:10:04 +0200210#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
211
wdenkf12e5682003-07-07 20:07:54 +0000212/*-----------------------------------------------------------------------
213 * Hardware Information Block
214 */
215#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
216#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
217#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
218
219/*-----------------------------------------------------------------------
220 * Cache Configuration
221 */
222#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500223#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000224#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
225#endif
226
227/*-----------------------------------------------------------------------
228 * SYPCR - System Protection Control 11-9
229 * SYPCR can only be written once after reset!
230 *-----------------------------------------------------------------------
231 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
232 */
233#if defined(CONFIG_WATCHDOG)
234#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
235 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
236#else
237#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
238#endif
239
240/*-----------------------------------------------------------------------
241 * SIUMCR - SIU Module Configuration 11-6
242 *-----------------------------------------------------------------------
243 * PCMCIA config., multi-function pin tri-state
244 */
245#ifndef CONFIG_CAN_DRIVER
246#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
247#else /* we must activate GPL5 in the SIUMCR for CAN */
248#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
249#endif /* CONFIG_CAN_DRIVER */
250
251/*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
255 */
256#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
257
258/*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 11-27
260 *-----------------------------------------------------------------------
261 */
262#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263
264/*-----------------------------------------------------------------------
265 * PISCR - Periodic Interrupt Status and Control 11-31
266 *-----------------------------------------------------------------------
267 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 */
269#define CFG_PISCR (PISCR_PS | PISCR_PITF)
270
271/*-----------------------------------------------------------------------
272 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
273 *-----------------------------------------------------------------------
274 * Reset PLL lock status sticky bit, timer expired status bit and timer
275 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000276 */
wdenkf12e5682003-07-07 20:07:54 +0000277#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000278
279/*-----------------------------------------------------------------------
280 * SCCR - System Clock and reset Control Register 15-27
281 *-----------------------------------------------------------------------
282 * Set clock output, timebase and RTC source and divider,
283 * power management and some other internal clocks
284 */
285#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000286#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000287 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
288 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000289
290/*-----------------------------------------------------------------------
291 * PCMCIA stuff
292 *-----------------------------------------------------------------------
293 *
294 */
295#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
296#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
297#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
298#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
299#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
300#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
301#define CFG_PCMCIA_IO_ADDR (0xEC000000)
302#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
303
304/*-----------------------------------------------------------------------
305 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
306 *-----------------------------------------------------------------------
307 */
308
309#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
310
311#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
312#undef CONFIG_IDE_LED /* LED for ide not supported */
313#undef CONFIG_IDE_RESET /* reset for ide not supported */
314
315#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
316#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
317
318#define CFG_ATA_IDE0_OFFSET 0x0000
319
320#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
321
322/* Offset for data I/O */
323#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
324
325/* Offset for normal register accesses */
326#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
327
328/* Offset for alternate registers */
329#define CFG_ATA_ALT_OFFSET 0x0100
330
331/*-----------------------------------------------------------------------
332 *
333 *-----------------------------------------------------------------------
334 *
335 */
336#define CFG_DER 0
337
338/*
339 * Init Memory Controller:
340 *
341 * BR0/1 and OR0/1 (FLASH)
342 */
343
344#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
345#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
346
347/* used to re-map FLASH both when starting from SRAM or FLASH:
348 * restrict access enough to keep SRAM working (if any)
349 * but not too much to meddle with FLASH accesses
350 */
351#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
352#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
353
354/*
355 * FLASH timing:
356 */
wdenkf12e5682003-07-07 20:07:54 +0000357#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
358 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000359
360#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
361#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
362#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
363
364#define CFG_OR1_REMAP CFG_OR0_REMAP
365#define CFG_OR1_PRELIM CFG_OR0_PRELIM
366#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
367
368/*
369 * BR2/3 and OR2/3 (SDRAM)
370 *
371 */
372#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
373#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
Jens Gehrleindabad4b2007-09-27 14:54:46 +0200374#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
wdenkf12e5682003-07-07 20:07:54 +0000375
376/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
377#define CFG_OR_TIMING_SDRAM 0x00000A00
378
379#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
380#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
381
382#ifndef CONFIG_CAN_DRIVER
383#define CFG_OR3_PRELIM CFG_OR2_PRELIM
384#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
385#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
386#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
387#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
388#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
389#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
390 BR_PS_8 | BR_MS_UPMB | BR_V )
391#endif /* CONFIG_CAN_DRIVER */
392
393/*
394 * Memory Periodic Timer Prescaler
395 *
396 * The Divider for PTA (refresh timer) configuration is based on an
397 * example SDRAM configuration (64 MBit, one bank). The adjustment to
398 * the number of chip selects (NCS) and the actually needed refresh
399 * rate is done by setting MPTPR.
400 *
401 * PTA is calculated from
402 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
403 *
404 * gclk CPU clock (not bus clock!)
405 * Trefresh Refresh cycle * 4 (four word bursts used)
406 *
407 * 4096 Rows from SDRAM example configuration
408 * 1000 factor s -> ms
409 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
410 * 4 Number of refresh cycles per period
411 * 64 Refresh cycle in ms per number of rows
412 * --------------------------------------------
413 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
414 *
415 * 50 MHz => 50.000.000 / Divider = 98
416 * 66 Mhz => 66.000.000 / Divider = 129
417 * 80 Mhz => 80.000.000 / Divider = 156
418 */
wdenke9132ea2004-04-24 23:23:30 +0000419
420#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
421#define CFG_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000422
423/*
424 * For 16 MBit, refresh rates could be 31.3 us
425 * (= 64 ms / 2K = 125 / quad bursts).
426 * For a simpler initialization, 15.6 us is used instead.
427 *
428 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
429 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
430 */
431#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
432#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
433
434/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
435#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
436#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
437
438/*
439 * MAMR settings for SDRAM
440 */
441
442/* 8 column SDRAM */
443#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
444 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
445 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
446/* 9 column SDRAM */
447#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
448 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
449 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
Jens Gehrleindabad4b2007-09-27 14:54:46 +0200450/* 10 column SDRAM */
451#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
452 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
453 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkf12e5682003-07-07 20:07:54 +0000454
455/*
456 * Internal Definitions
457 *
458 * Boot Flags
459 */
460#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
461#define BOOTFLAG_WARM 0x02 /* Software reboot */
462
463#define CONFIG_SCC1_ENET
464#define CONFIG_FEC_ENET
465#define CONFIG_ETHPRIME "SCC ETHERNET"
466
467#endif /* __CONFIG_H */