blob: c975a249c74fe5654dbf46226a4588728fa671ca [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Detlev Zundela99715b2008-04-18 14:50:01 +02002 * (C) Copyright 2007, 2008 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * ADS5121 board configuration file
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Rafal Jaworowski8993e542007-07-27 14:43:59 +020030/*
31 * Memory map for the ADS5121 board:
32 *
33 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
34 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
35 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
36 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070037 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
38 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
39 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020040 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
41 */
42
43/*
44 * High Level Configuration Options
45 */
46#define CONFIG_E300 1 /* E300 Family */
47#define CONFIG_MPC512X 1 /* MPC512X family */
York Sun0e1bad42008-05-05 10:20:01 -050048#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
49
50/* video */
51#undef CONFIG_VIDEO
52
53#if defined(CONFIG_VIDEO)
54#define CONFIG_CFB_CONSOLE
55#define CONFIG_VGA_AS_SINGLE_DEVICE
56#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020057
John Rigby5f91db72008-02-26 09:38:14 -070058/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020059
60#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
61
62#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050063#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020064
65#define CFG_IMMR 0x80000000
York Sun0e1bad42008-05-05 10:20:01 -050066#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020067
68#define CFG_MEMTEST_START 0x00200000 /* memtest region */
69#define CFG_MEMTEST_END 0x00400000
70
71/*
72 * DDR Setup - manually set all parameters as there's no SPD etc.
73 */
74#define CFG_DDR_SIZE 256 /* MB */
75#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
76#define CFG_SDRAM_BASE CFG_DDR_BASE
77
78/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020079 *
80 * SYS_CFG:
81 * [31:31] MDDRC Soft Reset: Diabled
82 * [30:30] DRAM CKE pin: Enabled
83 * [29:29] DRAM CLK: Enabled
84 * [28:28] Command Mode: Enabled (For initialization only)
85 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
86 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
87 * [20:19] Read Test: DON'T USE
88 * [18:18] Self Refresh: Enabled
89 * [17:17] 16bit Mode: Disabled
90 * [16:13] Ready Delay: 2
91 * [12:12] Half DQS Delay: Disabled
92 * [11:11] Quarter DQS Delay: Disabled
93 * [10:08] Write Delay: 2
94 * [07:07] Early ODT: Disabled
95 * [06:06] On DIE Termination: Disabled
96 * [05:05] FIFO Overflow Clear: DON'T USE here
97 * [04:04] FIFO Underflow Clear: DON'T USE here
98 * [03:03] FIFO Overflow Pending: DON'T USE here
99 * [02:02] FIFO Underlfow Pending: DON'T USE here
100 * [01:01] FIFO Overlfow Enabled: Enabled
101 * [00:00] FIFO Underflow Enabled: Enabled
102 * TIME_CFG0
103 * [31:16] DRAM Refresh Time: 0 CSB clocks
104 * [15:8] DRAM Command Time: 0 CSB clocks
105 * [07:00] DRAM Precharge Time: 0 CSB clocks
106 * TIME_CFG1
107 * [31:26] DRAM tRFC:
108 * [25:21] DRAM tWR1:
109 * [20:17] DRAM tWRT1:
110 * [16:11] DRAM tDRR:
111 * [10:05] DRAM tRC:
112 * [04:00] DRAM tRAS:
113 * TIME_CFG2
114 * [31:28] DRAM tRCD:
115 * [27:23] DRAM tFAW:
116 * [22:19] DRAM tRTW1:
117 * [18:15] DRAM tCCD:
118 * [14:10] DRAM tRTP:
119 * [09:05] DRAM tRP:
120 * [04:00] DRAM tRPA
121 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200122
Grzegorz Bernacki37e3c622008-01-28 10:15:02 +0100123#define CFG_MDDRC_SYS_CFG 0xF8604A00
124#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
125#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
126#define CFG_MDDRC_TIME_CFG0 0x00003D2E
127#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200128#define CFG_MDDRC_TIME_CFG1 0x54EC1168
129#define CFG_MDDRC_TIME_CFG2 0x35210864
130
131#define CFG_MICRON_NOP 0x01380000
132#define CFG_MICRON_PCHG_ALL 0x01100400
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200133#define CFG_MICRON_EM2 0x01020000
134#define CFG_MICRON_EM3 0x01030000
135#define CFG_MICRON_EN_DLL 0x01010000
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200136#define CFG_MICRON_RFSH 0x01080000
Grzegorz Bernacki37e3c622008-01-28 10:15:02 +0100137#define CFG_MICRON_INIT_DEV_OP 0x01000432
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200138#define CFG_MICRON_OCD_DEFAULT 0x01010780
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200139
140/* DDR Priority Manager Configuration */
York Sun0e1bad42008-05-05 10:20:01 -0500141#define CFG_MDDRCGRP_PM_CFG1 0x00077777
142#define CFG_MDDRCGRP_PM_CFG2 0x00000000
143#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
144#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
145#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
146#define CFG_MDDRCGRP_LUT1_MU 0x66666666
147#define CFG_MDDRCGRP_LUT1_ML 0x55555555
148#define CFG_MDDRCGRP_LUT2_MU 0x44444444
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200149#define CFG_MDDRCGRP_LUT2_ML 0x44444444
York Sun0e1bad42008-05-05 10:20:01 -0500150#define CFG_MDDRCGRP_LUT3_MU 0x55555555
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200151#define CFG_MDDRCGRP_LUT3_ML 0x55555558
York Sun0e1bad42008-05-05 10:20:01 -0500152#define CFG_MDDRCGRP_LUT4_MU 0x11111111
153#define CFG_MDDRCGRP_LUT4_ML 0x11111122
154#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
155#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
156#define CFG_MDDRCGRP_LUT1_AU 0x66666666
157#define CFG_MDDRCGRP_LUT1_AL 0x66666666
158#define CFG_MDDRCGRP_LUT2_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200159#define CFG_MDDRCGRP_LUT2_AL 0x11111111
York Sun0e1bad42008-05-05 10:20:01 -0500160#define CFG_MDDRCGRP_LUT3_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200161#define CFG_MDDRCGRP_LUT3_AL 0x11111111
York Sun0e1bad42008-05-05 10:20:01 -0500162#define CFG_MDDRCGRP_LUT4_AU 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200163#define CFG_MDDRCGRP_LUT4_AL 0x11111111
164
165/*
166 * NOR FLASH on the Local Bus
167 */
168#define CFG_FLASH_CFI /* use the Common Flash Interface */
169#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
170#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
171#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
172#define CFG_FLASH_USE_BUFFER_WRITE
173
174#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200175#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200176#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
177
178#undef CFG_FLASH_CHECKSUM
179
180/*
181 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
182 * window is 64KB
183 */
184#define CFG_CPLD_BASE 0x82000000
185#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
186
187#define CFG_SRAM_BASE 0x30000000
188#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
189
190#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
191#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
192
193/* Use SRAM for initial stack */
194#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
195#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
196
197#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
198#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
199#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
200
201#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
202#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500203#ifdef CONFIG_FSL_DIU_FB
204#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
205#else
206#define CFG_MALLOC_LEN (512 * 1024)
207#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200208
209/*
210 * Serial Port
211 */
212#define CONFIG_CONS_INDEX 1
213#undef CONFIG_SERIAL_SOFTWARE_FIFO
214
215/*
216 * Serial console configuration
217 */
218#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
219#if CONFIG_PSC_CONSOLE != 3
220#error CONFIG_PSC_CONSOLE must be 3
221#endif
222#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
223#define CFG_BAUDRATE_TABLE \
224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
225
226#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
227#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
228#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
229#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
230
231#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
232/* Use the HUSH parser */
233#define CFG_HUSH_PARSER
234#ifdef CFG_HUSH_PARSER
235#define CFG_PROMPT_HUSH_PS2 "> "
236#endif
237
John Rigby5f91db72008-02-26 09:38:14 -0700238/*
239 * PCI
240 */
241#ifdef CONFIG_PCI
242
243/*
244 * General PCI
245 */
246#define CFG_PCI_MEM_BASE 0xA0000000
247#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
248#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
249#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
250#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
251#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
252#define CFG_PCI_IO_BASE 0x00000000
253#define CFG_PCI_IO_PHYS 0x84000000
254#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
255
256
257#define CONFIG_PCI_PNP /* do pci plug-and-play */
258
259#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
260
261#endif
262
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200263/* I2C */
264#define CONFIG_HARD_I2C /* I2C with hardware support */
265#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
266#define CONFIG_I2C_MULTI_BUS
267#define CONFIG_I2C_CMD_TREE
268#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
269#define CFG_I2C_SLAVE 0x7F
270#if 0
Wolfgang Denkcf5933b2007-12-06 10:21:03 +0100271#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200272#endif
273
274/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200275 * EEPROM configuration
276 */
277#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
278#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
Wolfgang Denkde74b9e2007-10-13 21:15:39 +0200279#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200280#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
281
282/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200283 * Ethernet configuration
284 */
285#define CONFIG_MPC512x_FEC 1
286#define CONFIG_NET_MULTI
287#define CONFIG_PHY_ADDR 0x1
288#define CONFIG_MII 1 /* MII PHY management */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200289
290#if 0
291/*
292 * Configure on-board RTC
293 */
294#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
295#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
296#endif
297
298/*
299 * Environment
300 */
301#define CFG_ENV_IS_IN_FLASH 1
302/* This has to be a multiple of the Flash sector size */
303#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
304#define CFG_ENV_SIZE 0x2000
305#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
306
307/* Address and size of Redundant Environment Sector */
308#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
309#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
310
311#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
312#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
313
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200314#include <config_cmd_default.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200315
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200316#define CONFIG_CMD_ASKENV
317#define CONFIG_CMD_DHCP
318#define CONFIG_CMD_I2C
319#define CONFIG_CMD_MII
320#define CONFIG_CMD_NFS
321#define CONFIG_CMD_PING
322#define CONFIG_CMD_REGINFO
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200323#define CONFIG_CMD_EEPROM
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200324
325#if defined(CONFIG_PCI)
326#define CONFIG_CMD_PCI
327#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200328
329/*
330 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
331 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
332 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
333 * to chapter 36 of the MPC5121e Reference Manual.
334 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100335/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200336#define CFG_WATCHDOG_VALUE 0xFFFF
337
338 /*
339 * Miscellaneous configurable options
340 */
341#define CFG_LONGHELP /* undef to save memory */
342#define CFG_LOAD_ADDR 0x2000000 /* default load address */
343#define CFG_PROMPT "=> " /* Monitor Command Prompt */
344
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200345#ifdef CONFIG_CMD_KGDB
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100346 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200347#else
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100348 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200349#endif
350
351
352#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
353#define CFG_MAXARGS 16 /* max number of command args */
354#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
355#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
356
357/*
358 * For booting Linux, the board info and command line data
359 * have to be in the first 8 MB of memory, since this is
360 * the maximum mapped by the Linux kernel during initialization.
361 */
362#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
363
364/* Cache Configuration */
365#define CFG_DCACHE_SIZE 32768
366#define CFG_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200367#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200368#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
369#endif
370
371#define CFG_HID0_INIT 0x000000000
372#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
373#define CFG_HID2 HID2_HBE
374
375/*
376 * Internal Definitions
377 *
378 * Boot Flags
379 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100380#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
381#define BOOTFLAG_WARM 0x02 /* Software reboot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200382
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200383#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200384#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
385#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
386#endif
387
388/*
389 * Environment Configuration
390 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100391#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200392
393#define CONFIG_HOSTNAME ads5121
Wolfgang Denk8d103072008-01-13 23:37:50 +0100394#define CONFIG_BOOTFILE ads5121/uImage
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100395#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200396
Wolfgang Denk8d103072008-01-13 23:37:50 +0100397#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200398
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200399#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200400#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
401
402#define CONFIG_BAUDRATE 115200
403
404#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100405 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200406 "echo"
407
408#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100409 "u-boot_addr_r=200000\0" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100410 "kernel_addr_r=300000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100411 "fdt_addr_r=400000\0" \
412 "ramdisk_addr_r=500000\0" \
413 "u-boot_addr=FFF00000\0" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100414 "kernel_addr=FC040000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100415 "fdt_addr=FC2C0000\0" \
416 "ramdisk_addr=FC300000\0" \
417 "ramdiskfile=ads5121/uRamdisk\0" \
418 "fdtfile=ads5121/ads5121.dtb\0" \
419 "u-boot=ads5121/u-boot.bin\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200420 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100421 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200422 "nfsargs=setenv bootargs root=/dev/nfs rw " \
423 "nfsroot=${serverip}:${rootpath}\0" \
424 "ramargs=setenv bootargs root=/dev/ram rw\0" \
425 "addip=setenv bootargs ${bootargs} " \
426 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
427 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100428 "addtty=setenv bootargs ${bootargs} " \
429 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200430 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200431 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200432 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100433 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
434 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
435 "tftp ${fdt_addr_r} ${fdtfile};" \
436 "run nfsargs addip addtty;" \
437 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
438 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
439 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200440 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100441 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100442 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200443 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100444 "update=protect off ${u-boot_addr} +${filesize};" \
445 "era ${u-boot_addr} +${filesize};" \
446 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
447 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200448 ""
449
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200450#define CONFIG_BOOTCOMMAND "run flash_self"
451
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100452#define CONFIG_OF_LIBFDT 1
453#define CONFIG_OF_BOARD_SETUP 1
454
455#define OF_CPU "PowerPC,5121@0"
John Rigbyac915282008-01-30 13:36:57 -0700456#define OF_SOC "soc@80000000"
457#define OF_SOC_OLD "soc5121@80000000"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100458#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700459#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100460
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200461#endif /* __CONFIG_H */