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Niklaus Giger75a66dc2008-02-25 18:46:42 +01001/*
2 *(C) Copyright 2005-2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
26 ***********************************************************************/
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34#define CONFIG_MCU25 1 /* Board is MCU25 */
35#define CONFIG_4xx 1 /* ... PPC4xx family */
36#define CONFIG_405GP 1
37#define CONFIG_4xx 1
38
39#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
43
44/*-----------------------------------------------------------------------
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47*----------------------------------------------------------------------*/
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
Niklaus Giger75a66dc2008-02-25 18:46:42 +010049#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
50
51
52#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
53#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
54#define CFG_MONITOR_BASE TEXT_BASE
55
56/* ... with on-chip memory here (4KBytes) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020057#define CFG_OCM_DATA_ADDR 0xF4000000
58#define CFG_OCM_DATA_SIZE 0x00001000
Niklaus Giger75a66dc2008-02-25 18:46:42 +010059/* Do not set up locked dcache as init ram. */
60#undef CFG_INIT_DCACHE_CS
61
62/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020063#define CFG_TEMP_STACK_OCM 1
Niklaus Giger75a66dc2008-02-25 18:46:42 +010064
65#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
66#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
67#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
68#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
69#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
70
71/*-----------------------------------------------------------------------
72 * Serial Port
73 *----------------------------------------------------------------------*/
74/*
75 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
76 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
77 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
78 * The Linux BASE_BAUD define should match this configuration.
79 * baseBaud = cpuClock/(uartDivisor*16)
80 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
81 * set Linux BASE_BAUD to 403200.
82 */
83#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
84#define CONFIG_SERIAL_MULTI 1
85/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
86#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
87#define CFG_BASE_BAUD 691200
88
89/* Size (bytes) of interrupt driven serial port buffer.
90 * Set to 0 to use polling instead of interrupts.
91 * Setting to 0 will also disable RTS/CTS handshaking.
92 */
93#undef CONFIG_SERIAL_SOFTWARE_FIFO
94
95/* Set console baudrate to 9600 */
96#define CONFIG_BAUDRATE 9600
97
98
99#define CFG_BAUDRATE_TABLE \
100 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
101
102/*-----------------------------------------------------------------------
103 * Flash
104 *----------------------------------------------------------------------*/
105
106/* Use common CFI driver */
107#define CFG_FLASH_CFI
108#define CFG_FLASH_CFI_DRIVER
109/* board provides its own flash_init code */
110#define CONFIG_FLASH_CFI_LEGACY 1
111#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
112#define CFG_FLASH_LEGACY_512Kx8 1
113
114/* print 'E' for empty sector on flinfo */
115#define CFG_FLASH_EMPTY_INFO
116
117#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
118#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
119
120/*-----------------------------------------------------------------------
121 * Environment
122 *----------------------------------------------------------------------*/
123
124#undef CFG_ENV_IS_IN_NVRAM
125#define CFG_ENV_IS_IN_FLASH
126#undef CFG_ENV_IS_NOWHERE
127
128#ifdef CFG_ENV_IS_IN_EEPROM
129/* Put the environment after the SDRAM configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130#define PROM_SIZE 2048
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100131#define CFG_ENV_OFFSET 512
132#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
133#endif
134
135#ifdef CFG_ENV_IS_IN_FLASH
136/* Put the environment in Flash */
137#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
138#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
139#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
140
141/* Address and size of Redundant Environment Sector */
142#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
143#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
144#endif
145
146/*-----------------------------------------------------------------------
147 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
148 * the first internal I2C controller of the PPC440EPx
149 *----------------------------------------------------------------------*/
150#define CFG_SPD_BUS_NUM 0
151
152#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
153#undef CONFIG_SOFT_I2C /* I2C bit-banged */
154#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
155#define CFG_I2C_SLAVE 0x7F
156
157/* This is the 7bit address of the device, not including P. */
158#define CFG_I2C_EEPROM_ADDR 0x50
159#define CFG_I2C_EEPROM_ADDR_LEN 1
160
161/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
162#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
163#define CFG_EEPROM_PAGE_WRITE_BITS 4
164#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
165#define CFG_EEPROM_PAGE_WRITE_ENABLE
166#undef CFG_I2C_MULTI_EEPROMS
167
168
169#define CONFIG_PREBOOT "echo;" \
170 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
171 "echo"
172
173#undef CONFIG_BOOTARGS
174
175/* Setup some board specific values for the default environment variables */
176#define CONFIG_HOSTNAME mcu25
177#define CONFIG_IPADDR 172.25.1.99
178#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
179#define CONFIG_OVERWRITE_ETHADDR_ONCE
180#define CONFIG_SERVERIP 172.25.1.3
181
182#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
183
184#define CONFIG_EXTRA_ENV_SETTINGS \
185 "netdev=eth0\0" \
186 "loadaddr=0x01000000\0" \
187 "nfsargs=setenv bootargs root=/dev/nfs rw " \
188 "nfsroot=${serverip}:${rootpath}\0" \
189 "ramargs=setenv bootargs root=/dev/ram rw\0" \
190 "addip=setenv bootargs ${bootargs} " \
191 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
192 ":${hostname}:${netdev}:off panic=1\0" \
193 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
194 "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
195 "bootm\0" \
196 "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
197 "bootfile=/tftpboot/mcu25/uImage\0" \
198 "load=tftp 100000 mcu25/u-boot.bin\0" \
199 "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
200 "cp.b 100000 FFFB0000 50000\0" \
201 "upd=run load;run update\0" \
202 "vx_rom=mcu25/mcu25_vx_rom\0" \
203 "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
204 "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
205 " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
206 ""
207#define CONFIG_BOOTCOMMAND "run vx"
208
209#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
210
211#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
212#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
213
214#define CONFIG_MII 1 /* MII PHY management */
215#define CONFIG_PHY_ADDR 1 /* PHY address */
216
217#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
218
219#define CONFIG_HAS_ETH0
220#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descr */
221
222/*
223 * BOOTP options
224 */
225#define CONFIG_BOOTP_BOOTFILESIZE
226#define CONFIG_BOOTP_BOOTPATH
227#define CONFIG_BOOTP_GATEWAY
228#define CONFIG_BOOTP_HOSTNAME
229
230/*
231 * Command line configuration.
232 */
233#include <config_cmd_default.h>
234
235#define CONFIG_CMD_ASKENV
236#define CONFIG_CMD_CACHE
237#define CONFIG_CMD_DHCP
238#define CONFIG_CMD_DIAG
239#define CONFIG_CMD_EEPROM
240#define CONFIG_CMD_ELF
241#define CONFIG_CMD_FLASH
242#define CONFIG_CMD_I2C
243#define CONFIG_CMD_IMMAP
244#define CONFIG_CMD_IRQ
245#define CONFIG_CMD_MII
246#define CONFIG_CMD_NET
247#define CONFIG_CMD_PING
248#define CONFIG_CMD_REGINFO
249#define CONFIG_CMD_SDRAM
250
251/* SPD EEPROM (sdram speed config) disabled */
252#define CONFIG_SPD_EEPROM 1
253#define SPD_EEPROM_ADDRESS 0x50
254
255/* POST support */
256#define CONFIG_POST (CFG_POST_MEMORY | \
257 CFG_POST_CPU | \
258 CFG_POST_UART | \
259 CFG_POST_I2C | \
260 CFG_POST_CACHE | \
261 CFG_POST_ETHER | \
262 CFG_POST_SPR)
263
264#define CFG_POST_UART_TABLE {UART0_BASE}
265#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
266#undef CONFIG_LOGBUFFER
267#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
268#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
269
270/*-----------------------------------------------------------------------
271 * Miscellaneous configurable options
272 *----------------------------------------------------------------------*/
273#define CFG_LONGHELP /* undef to save memory */
274#define CFG_PROMPT "=> " /* Monitor Command Prompt */
275#if defined(CONFIG_CMD_KGDB)
276 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
277#else
278 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
279#endif
280#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
281#define CFG_MAXARGS 16 /* max number of command args */
282#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
283
284#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
285#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
286
287
288#define CFG_LOAD_ADDR 0x100000 /* default load address */
289#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
290
291#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
292
293#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
294#define CONFIG_LOOPW 1 /* enable loopw command */
295#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
296
297/*-----------------------------------------------------------------------
298 * External Bus Controller (EBC) Setup
299 */
300
301#define CFG_EBC_CFG 0x98400000
302
303/* Memory Bank 0 (Flash Bank 0) initialization */
304#define CFG_EBC_PB0AP 0x02005400
305#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
306
307#define CFG_EBC_PB1AP 0x03041200
308#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
309
310#define CFG_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
311#define CFG_EBC_PB2CR 0x7A09A000u
312
313#define CFG_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
314#define CFG_EBC_PB3CR 0x7B09A000u
315
316#define CFG_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
317#define CFG_EBC_PB4CR 0x7C09A000u
318
319#define CFG_EBC_PB5AP 0x00800200u
320#define CFG_EBC_PB5CR 0x7D81A000u
321
322#define CFG_EBC_PB6AP 0x01040200u
323#define CFG_EBC_PB6CR 0x7D91A000u
324
325#define CFG_GPIO0_OR 0x087FFFFF /* GPIO value */
326#define CFG_GPIO0_TCR 0x7FFF8000 /* GPIO value */
327#define CFG_GPIO0_ODR 0xFFFF0000 /* GPIO value */
328/*
329 * For booting Linux, the board info and command line data
330 * have to be in the first 8 MB of memory, since this is
331 * the maximum mapped by the Linux kernel during initialization.
332 */
333#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
334
335/* Init Memory Controller:
336 *
337 * BR0/1 and OR0/1 (FLASH)
338 */
339
340#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
341#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
342
343
344/* Configuration Port location */
345#define CONFIG_PORT_ADDR 0xF0000500
346
347#define CFG_HUSH_PARSER /* use "hush" command parser */
348#ifdef CFG_HUSH_PARSER
349#define CFG_PROMPT_HUSH_PS2 "> "
350#endif
351
352#if defined(CONFIG_CMD_KGDB)
353#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
354#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
355#endif
356
357/* pass open firmware flat tree */
358#define CONFIG_OF_LIBFDT 1
359#define CONFIG_OF_BOARD_SETUP 1
360
361#endif /* __CONFIG_H */