wdenk | 5b1d713 | 2002-11-03 00:07:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Dave Ellis, SIXNET, dge@sixnetio.com |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 5b1d713 | 2002-11-03 00:07:02 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | Using the Motorola MPC8XXFADS development board |
| 9 | =============================================== |
| 10 | |
| 11 | CONFIGURATIONS |
| 12 | -------------- |
| 13 | |
| 14 | There are ready-to-use default configurations available for the |
| 15 | FADS823, FADS850SAR and FADS860T. The FADS860T configuration also |
| 16 | works for the 855T processor. |
| 17 | |
| 18 | LOADING U-Boot INTO FADS FLASH MEMORY |
| 19 | -------------------------------------- |
| 20 | |
| 21 | MPC8BUG can load U-Boot into the FLASH memory using LOADF. |
| 22 | |
| 23 | loadf u-boot.srec 100000 |
| 24 | |
| 25 | |
| 26 | STARTING U-Boot FROM MPC8BUG |
| 27 | ----------------------------- |
| 28 | |
| 29 | To start U-Boot from MPC8BUG: |
| 30 | |
| 31 | 1. Reset the board: |
| 32 | reset :h |
| 33 | |
| 34 | 2. Change BR0 and OR0 back to their values at reset: |
| 35 | rms memc br0 00000001 |
| 36 | rms memc or0 00000d34 |
| 37 | |
| 38 | 3. Modify DER so MPC8BUG gets control only when it should: |
| 39 | rms der 2002000f |
| 40 | |
| 41 | 4. Start as if from reset: |
| 42 | go 100 |
| 43 | |
| 44 | This is NOT exactly the same as starting U-Boot without |
| 45 | MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. |
| 46 | After it does the reset it writes SYPCR (to disable the watchdog) |
| 47 | and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots |
| 48 | of other initialization). That is why it is necessary to set BR0 |
| 49 | and OR0 to map the FLASH everywhere. U-Boot can't turn on the |
| 50 | watchdog after that, since MPC8BUG has used the only chance to write |
| 51 | to SYPCR. |
| 52 | |
| 53 | Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets |
| 54 | U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T |
| 55 | processor (your mileage may vary). It is probably better (and a lot |
| 56 | easier) just to accept having the watchdog disabled when the debug |
| 57 | cable is connected. |
| 58 | |
| 59 | in MPC8BUG: |
| 60 | reset :h |
| 61 | rms memc br0 00000001 |
| 62 | rms memc or0 00000d34 |
| 63 | rms der 2000f |
| 64 | go 100 |
| 65 | |
| 66 | Now U-Boot is running with the MPC8BUG value for SYPCR. Use the |
| 67 | U-Boot 'reset' command to reset the board. |
| 68 | =>reset |
| 69 | Next, in MPC8BUG: |
| 70 | rms der 2000f |
| 71 | go |
| 72 | |
| 73 | Now U-Boot is running with the U-Boot value for SYPCR. |