blob: 705cbfb5cb0861221f8b41086a3dfff43bb33ede [file] [log] [blame]
Jagan Teki09008402022-12-14 23:20:55 +05301{
2 {
3 {
4 .rank = 0x1,
5 .col = 0xB,
6 .bk = 0x3,
7 .bw = 0x1,
8 .dbw = 0x1,
9 .row_3_4 = 0x0,
10 .cs0_row = 0x11,
11 .cs1_row = 0x11,
12 .cs0_high16bit_row = 0x0,
13 .cs1_high16bit_row = 0x0,
14 .ddrconfig = 0
15 },
16 {
17 {0x41241522},
18 {0x15050b07},
19 {0x00000602},
20 {0x00001111},
21 {0x00000054},
22 {0x00000000},
23 0x000000ff
24 }
25 },
26 {
27 .ddr_freq = 1056, /* clock rate(MHz) */
28 .dramtype = LPDDR4,
29 .num_channels = 1,
30 .stride = 0,
31 .odt = 1
32 },
33 {
34 {
35 {0x00000000, 0x81081020}, /* MSTR */
36 {0x00000064, 0x00400094}, /* RFSHTMG */
37 {0x000000d0, 0x00030409}, /* INIT0 */
38 {0x000000d4, 0x00690000}, /* INIT1 */
39 {0x000000d8, 0x00000206}, /* INIT2 */
40 {0x000000dc, 0x0034001b}, /* INIT3 */
41 {0x000000e0, 0x00310000}, /* INIT4 */
42 {0x000000e8, 0x00110000}, /* INIT6 */
43 {0x000000ec, 0x00000000}, /* INIT7 */
44 {0x000000f4, 0x000f033f}, /* RANKCTL */
45 {0x00000100, 0x14161217}, /* DRAMTMG0 */
46 {0x00000104, 0x00040422}, /* DRAMTMG1 */
47 {0x00000108, 0x050a0e0f}, /* DRAMTMG2 */
48 {0x0000010c, 0x00808000}, /* DRAMTMG3 */
49 {0x00000110, 0x0a04060c}, /* DRAMTMG4 */
50 {0x00000114, 0x02040808}, /* DRAMTMG5 */
51 {0x00000118, 0x01010005}, /* DRAMTMG6 */
52 {0x0000011c, 0x00000401}, /* DRAMTMG7 */
53 {0x00000120, 0x00000606}, /* DRAMTMG8 */
54 {0x00000130, 0x00020000}, /* DRAMTMG12 */
55 {0x00000134, 0x0a100002}, /* DRAMTMG13 */
56 {0x00000138, 0x00000098}, /* DRAMTMG14 */
57 {0x00000180, 0x02100010}, /* ZQCTL0 */
58 {0x00000184, 0x01b00000}, /* ZQCTL1 */
59 {0x00000190, 0x07070001}, /* DFITMG0 */
60 {0x00000198, 0x07000101}, /* DFILPCFG0 */
61 {0x000001a0, 0xc0400003}, /* DFIUPD0 */
62 {0x00000240, 0x0b050d3c}, /* ODTCFG */
63 {0x00000244, 0x00000101}, /* ODTMAP */
64 {0x00000250, 0x00001f00}, /* SCHED */
65 {0x00000490, 0x00000001}, /* PCTRL_0 */
66 {0xffffffff, 0xffffffff}
67 }
68 },
69 {
70 {
71 {0x00000004, 0x0000008d}, /* PHYREG01 */
72 {0x00000014, 0x00000014}, /* PHYREG05 */
73 {0x00000018, 0x00000000}, /* PHYREG06 */
74 {0x0000001c, 0x0000000a}, /* PHYREG07 */
75 {0xffffffff, 0xffffffff}
76 }
77 }
78},