Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tom Warren | efc05ae | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 2 | /* |
Tom Warren | 52a8b82 | 2012-05-22 12:19:25 +0000 | [diff] [blame] | 3 | * (C) Copyright 2010-2012 |
Tom Warren | efc05ae | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 4 | * NVIDIA Corporation <www.nvidia.com> |
Tom Warren | efc05ae | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 7 | #ifndef _TEGRA20_COMMON_H_ |
| 8 | #define _TEGRA20_COMMON_H_ |
| 9 | #include "tegra-common.h" |
| 10 | |
| 11 | /* |
| 12 | * NS16550 Configuration |
| 13 | */ |
| 14 | #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ |
Simon Glass | 649d0ff | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 15 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 16 | /* |
| 17 | * Miscellaneous configurable options |
| 18 | */ |
Jonathan Hunter | f16e311 | 2019-02-12 16:03:14 +0000 | [diff] [blame] | 19 | #define CONFIG_STACKBASE 0x03800000 /* 56MB */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 20 | |
| 21 | /*----------------------------------------------------------------------- |
| 22 | * Physical Memory Map |
| 23 | */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * Memory layout for where various images get loaded by boot scripts: |
| 27 | * |
| 28 | * scriptaddr can be pretty much anywhere that doesn't conflict with something |
| 29 | * else. Put it above BOOTMAPSZ to eliminate conflicts. |
| 30 | * |
Stephen Warren | f940c72 | 2014-02-05 09:24:59 -0700 | [diff] [blame] | 31 | * pxefile_addr_r can be pretty much anywhere that doesn't conflict with |
| 32 | * something else. Put it above BOOTMAPSZ to eliminate conflicts. |
| 33 | * |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 34 | * kernel_addr_r must be within the first 128M of RAM in order for the |
| 35 | * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will |
| 36 | * decompress itself to 0x8000 after the start of RAM, kernel_addr_r |
| 37 | * should not overlap that area, or the kernel will have to copy itself |
| 38 | * somewhere else before decompression. Similarly, the address of any other |
| 39 | * data passed to the kernel shouldn't overlap the start of RAM. Pushing |
Jonathan Hunter | f16e311 | 2019-02-12 16:03:14 +0000 | [diff] [blame] | 40 | * this up to 32M allows for a sizable kernel to be decompressed below the |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 41 | * compressed load address. |
| 42 | * |
Jonathan Hunter | f16e311 | 2019-02-12 16:03:14 +0000 | [diff] [blame] | 43 | * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for |
| 44 | * the compressed kernel to be up to 32M too. |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 45 | * |
Jonathan Hunter | f16e311 | 2019-02-12 16:03:14 +0000 | [diff] [blame] | 46 | * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 47 | * for the FDT/DTB to be up to 1M, which is hopefully plenty. |
| 48 | */ |
| 49 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 50 | "scriptaddr=0x10000000\0" \ |
Stephen Warren | f940c72 | 2014-02-05 09:24:59 -0700 | [diff] [blame] | 51 | "pxefile_addr_r=0x10100000\0" \ |
Tom Rini | 72d8136 | 2021-08-23 10:25:30 -0400 | [diff] [blame] | 52 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
Peter Robinson | 632fb97 | 2020-04-02 00:28:54 +0100 | [diff] [blame] | 53 | "fdtfile=" FDTFILE "\0" \ |
Jonathan Hunter | f16e311 | 2019-02-12 16:03:14 +0000 | [diff] [blame] | 54 | "fdt_addr_r=0x03000000\0" \ |
| 55 | "ramdisk_addr_r=0x03100000\0" |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 56 | |
| 57 | /* Defines for SPL */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 58 | #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 |
| 59 | #define CONFIG_SPL_STACK 0x000ffffc |
| 60 | |
Simon Glass | ad16617 | 2012-10-17 13:24:56 +0000 | [diff] [blame] | 61 | /* Align LCD to 1MB boundary */ |
| 62 | #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE |
| 63 | |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 64 | #ifdef CONFIG_TEGRA_LP0 |
Simon Glass | 649d0ff | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 65 | #define TEGRA_LP0_ADDR 0x1C406000 |
| 66 | #define TEGRA_LP0_SIZE 0x2000 |
| 67 | #define TEGRA_LP0_VEC \ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 68 | "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ |
Marek Vasut | 51926d5 | 2012-09-23 17:41:25 +0200 | [diff] [blame] | 69 | "@" __stringify(TEGRA_LP0_ADDR) " " |
Simon Glass | 649d0ff | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 70 | #else |
| 71 | #define TEGRA_LP0_VEC |
| 72 | #endif |
| 73 | |
Simon Glass | 0291091 | 2012-02-27 10:52:51 +0000 | [diff] [blame] | 74 | /* |
| 75 | * This parameter affects a TXFILLTUNING field that controls how much data is |
| 76 | * sent to the latency fifo before it is sent to the wire. Without this |
| 77 | * parameter, the default (2) causes occasional Data Buffer Errors in OUT |
| 78 | * packets depending on the buffer address and size. |
| 79 | */ |
Peter Robinson | cba0ae6 | 2018-09-16 18:22:58 +0100 | [diff] [blame] | 80 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 |
Simon Glass | 0291091 | 2012-02-27 10:52:51 +0000 | [diff] [blame] | 81 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 82 | #endif /* _TEGRA20_COMMON_H_ */ |