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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Eibach60083262017-02-22 16:07:23 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
Dirk Eibach60083262017-02-22 16:07:23 +01005 */
6
7#ifndef _CONFIG_CONTROLCENTERDC_H
8#define _CONFIG_CONTROLCENTERDC_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
13#define CONFIG_CUSTOMER_BOARD_SUPPORT
14
Dirk Eibach60083262017-02-22 16:07:23 +010015/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
Dirk Eibach60083262017-02-22 16:07:23 +010020
Dirk Eibach60083262017-02-22 16:07:23 +010021/*
Dirk Eibach60083262017-02-22 16:07:23 +010022 * SATA/SCSI/AHCI configuration
23 */
Dirk Eibach60083262017-02-22 16:07:23 +010024#define CONFIG_SCSI_AHCI_PLAT
25#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
26#define CONFIG_SYS_SCSI_MAX_LUN 1
27#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
28 CONFIG_SYS_SCSI_MAX_LUN)
29
Dirk Eibach60083262017-02-22 16:07:23 +010030/* USB/EHCI configuration */
31#define CONFIG_EHCI_IS_TDI
32
33/* Environment in SPI NOR flash */
Dirk Eibach60083262017-02-22 16:07:23 +010034
Dirk Eibach60083262017-02-22 16:07:23 +010035#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
36
37/* PCIe support */
38#ifndef CONFIG_SPL_BUILD
Dirk Eibach60083262017-02-22 16:07:23 +010039#define CONFIG_PCI_SCAN_SHOW
40#endif
41
Dirk Eibach60083262017-02-22 16:07:23 +010042/*
43 * Software (bit-bang) MII driver configuration
44 */
Dirk Eibach60083262017-02-22 16:07:23 +010045#define CONFIG_BITBANGMII_MULTI
46
47/* SPL */
48/*
49 * Select the boot device here
50 *
51 * Currently supported are:
52 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
53 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
54 */
55#define SPL_BOOT_SPI_NOR_FLASH 1
56#define SPL_BOOT_SDIO_MMC_CARD 2
57#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
58
59/* Defines for SPL */
Dirk Eibach60083262017-02-22 16:07:23 +010060#define CONFIG_SPL_SIZE (160 << 10)
61
62#if defined(CONFIG_SECURED_MODE_IMAGE)
Dirk Eibach60083262017-02-22 16:07:23 +010063#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
64#else
Dirk Eibach60083262017-02-22 16:07:23 +010065#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
66#endif
67
68#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
69#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
70
71#ifdef CONFIG_SPL_BUILD
72#define CONFIG_SYS_MALLOC_SIMPLE
73#endif
74
75#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
76#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
77
78#define CONFIG_SPL_LIBCOMMON_SUPPORT
79#define CONFIG_SPL_LIBGENERIC_SUPPORT
Simon Glass975e7cf2021-07-10 21:14:36 -060080#define CONFIG_SPL_I2C
Dirk Eibach60083262017-02-22 16:07:23 +010081
Dirk Eibach60083262017-02-22 16:07:23 +010082#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
83/* SPL related MMC defines */
Simon Glass103c5f12021-08-08 12:20:09 -060084#define CONFIG_SPL_MMC
Dirk Eibach60083262017-02-22 16:07:23 +010085#ifdef CONFIG_SPL_BUILD
86#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
87#endif
88#endif
89
90/*
91 * Environment Configuration
92 */
Dirk Eibach60083262017-02-22 16:07:23 +010093
Mario Six5bc05432018-03-28 14:38:20 +020094#define CONFIG_HOSTNAME "ccdc"
Dirk Eibach60083262017-02-22 16:07:23 +010095#define CONFIG_ROOTPATH "/opt/nfsroot"
96#define CONFIG_BOOTFILE "ccdc.img"
97
Dirk Eibach60083262017-02-22 16:07:23 +010098#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth1\0" \
100 "consoledev=ttyS1\0" \
101 "u-boot=u-boot.bin\0" \
102 "bootfile_addr=1000000\0" \
103 "keyprogram_addr=3000000\0" \
104 "keyprogram_file=keyprogram.img\0" \
105 "fdtfile=controlcenterdc.dtb\0" \
106 "load=tftpboot ${loadaddr} ${u-boot}\0" \
107 "mmcdev=0:2\0" \
108 "update=sf probe 1:0;" \
109 " sf erase 0 +${filesize};" \
110 " sf write ${fileaddr} 0 ${filesize}\0" \
111 "upd=run load update\0" \
112 "fdt_high=0x10000000\0" \
113 "initrd_high=0x10000000\0" \
114 "loadkeyprogram=tpm flush_keys;" \
115 " mmc rescan;" \
116 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
117 " source ${keyprogram_addr}:script@1\0" \
118 "gpio1=gpio@22_25\0" \
119 "gpio2=A29\0" \
120 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
121 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
122 "bootfail=for i in ${blinkseq}; do" \
123 " if test $i -eq 0; then" \
124 " gpio clear ${gpio1}; gpio set ${gpio2};" \
125 " elif test $i -eq 1; then" \
126 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
127 " elif test $i -eq 2; then" \
128 " gpio set ${gpio1}; gpio set ${gpio2};" \
129 " else;" \
130 " gpio clear ${gpio1}; gpio set ${gpio2};" \
131 " fi; sleep 0.12; done\0"
132
Tom Rini7ae1b082021-08-19 14:29:00 -0400133#define NFSBOOTCOMMAND \
Dirk Eibach60083262017-02-22 16:07:23 +0100134 "setenv bootargs root=/dev/nfs rw " \
135 "nfsroot=${serverip}:${rootpath} " \
136 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
137 "console=${consoledev},${baudrate} ${othbootargs}; " \
138 "tftpboot ${bootfile_addr} ${bootfile}; " \
139 "bootm ${bootfile_addr}"
140
Tom Rini7ae1b082021-08-19 14:29:00 -0400141#define MMCBOOTCOMMAND \
Dirk Eibach60083262017-02-22 16:07:23 +0100142 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
143 "console=${consoledev},${baudrate} ${othbootargs}; " \
144 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
145 "bootm ${bootfile_addr}"
146
147#define CONFIG_BOOTCOMMAND \
148 "if env exists keyprogram; then;" \
149 " setenv keyprogram; run nfsboot;" \
150 " fi;" \
151 " run dobootfail"
152
153/*
154 * mv-common.h should be defined after CMD configs since it used them
155 * to enable certain macros
156 */
157#include "mv-common.h"
158
159#endif /* _CONFIG_CONTROLCENTERDC_H */