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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a375ff8e14bea0a5cbfff99d6456aa8d9a3320ab / . / arch / arm / mach-omap2 / omap5 / prcm-regs.c
blob: b5f1d700fd8e74edd6fe05b6ca291afc5f64954c [file] [log] [blame]
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]1/*
2 *
3 * HW regs data for OMAP5 Soc
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]11 */
12
13#include <asm/omap_common.h>
Nishanth Menon76cff2b2015-08-13 09:51:00 -0500[diff] [blame]14#include <asm/io.h>
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]15
16struct prcm_regs const omap5_es1_prcm = {
17 /* cm1.ckgen */
18 .cm_clksel_core = 0x4a004100,
19 .cm_clksel_abe = 0x4a004108,
20 .cm_dll_ctrl = 0x4a004110,
21 .cm_clkmode_dpll_core = 0x4a004120,
22 .cm_idlest_dpll_core = 0x4a004124,
23 .cm_autoidle_dpll_core = 0x4a004128,
24 .cm_clksel_dpll_core = 0x4a00412c,
25 .cm_div_m2_dpll_core = 0x4a004130,
26 .cm_div_m3_dpll_core = 0x4a004134,
27 .cm_div_h11_dpll_core = 0x4a004138,
28 .cm_div_h12_dpll_core = 0x4a00413c,
29 .cm_div_h13_dpll_core = 0x4a004140,
30 .cm_div_h14_dpll_core = 0x4a004144,
31 .cm_ssc_deltamstep_dpll_core = 0x4a004148,
32 .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
33 .cm_emu_override_dpll_core = 0x4a004150,
34 .cm_div_h22_dpllcore = 0x4a004154,
35 .cm_div_h23_dpll_core = 0x4a004158,
36 .cm_clkmode_dpll_mpu = 0x4a004160,
37 .cm_idlest_dpll_mpu = 0x4a004164,
38 .cm_autoidle_dpll_mpu = 0x4a004168,
39 .cm_clksel_dpll_mpu = 0x4a00416c,
40 .cm_div_m2_dpll_mpu = 0x4a004170,
41 .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
42 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
43 .cm_bypclk_dpll_mpu = 0x4a00419c,
44 .cm_clkmode_dpll_iva = 0x4a0041a0,
45 .cm_idlest_dpll_iva = 0x4a0041a4,
46 .cm_autoidle_dpll_iva = 0x4a0041a8,
47 .cm_clksel_dpll_iva = 0x4a0041ac,
48 .cm_div_h11_dpll_iva = 0x4a0041b8,
49 .cm_div_h12_dpll_iva = 0x4a0041bc,
50 .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
51 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
52 .cm_bypclk_dpll_iva = 0x4a0041dc,
53 .cm_clkmode_dpll_abe = 0x4a0041e0,
54 .cm_idlest_dpll_abe = 0x4a0041e4,
55 .cm_autoidle_dpll_abe = 0x4a0041e8,
56 .cm_clksel_dpll_abe = 0x4a0041ec,
57 .cm_div_m2_dpll_abe = 0x4a0041f0,
58 .cm_div_m3_dpll_abe = 0x4a0041f4,
59 .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
60 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
61 .cm_clkmode_dpll_ddrphy = 0x4a004220,
62 .cm_idlest_dpll_ddrphy = 0x4a004224,
63 .cm_autoidle_dpll_ddrphy = 0x4a004228,
64 .cm_clksel_dpll_ddrphy = 0x4a00422c,
65 .cm_div_m2_dpll_ddrphy = 0x4a004230,
66 .cm_div_h11_dpll_ddrphy = 0x4a004238,
67 .cm_div_h12_dpll_ddrphy = 0x4a00423c,
68 .cm_div_h13_dpll_ddrphy = 0x4a004240,
69 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
70 .cm_shadow_freq_config1 = 0x4a004260,
71 .cm_mpu_mpu_clkctrl = 0x4a004320,
72
73 /* cm1.dsp */
74 .cm_dsp_clkstctrl = 0x4a004400,
75 .cm_dsp_dsp_clkctrl = 0x4a004420,
76
77 /* cm1.abe */
78 .cm1_abe_clkstctrl = 0x4a004500,
79 .cm1_abe_l4abe_clkctrl = 0x4a004520,
80 .cm1_abe_aess_clkctrl = 0x4a004528,
81 .cm1_abe_pdm_clkctrl = 0x4a004530,
82 .cm1_abe_dmic_clkctrl = 0x4a004538,
83 .cm1_abe_mcasp_clkctrl = 0x4a004540,
84 .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
85 .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
86 .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
87 .cm1_abe_slimbus_clkctrl = 0x4a004560,
88 .cm1_abe_timer5_clkctrl = 0x4a004568,
89 .cm1_abe_timer6_clkctrl = 0x4a004570,
90 .cm1_abe_timer7_clkctrl = 0x4a004578,
91 .cm1_abe_timer8_clkctrl = 0x4a004580,
92 .cm1_abe_wdt3_clkctrl = 0x4a004588,
93
94 /* cm2.ckgen */
95 .cm_clksel_mpu_m3_iss_root = 0x4a008100,
96 .cm_clksel_usb_60mhz = 0x4a008104,
97 .cm_scale_fclk = 0x4a008108,
98 .cm_core_dvfs_perf1 = 0x4a008110,
99 .cm_core_dvfs_perf2 = 0x4a008114,
100 .cm_core_dvfs_perf3 = 0x4a008118,
101 .cm_core_dvfs_perf4 = 0x4a00811c,
102 .cm_core_dvfs_current = 0x4a008124,
103 .cm_iva_dvfs_perf_tesla = 0x4a008128,
104 .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
105 .cm_iva_dvfs_perf_abe = 0x4a008130,
106 .cm_iva_dvfs_current = 0x4a008138,
107 .cm_clkmode_dpll_per = 0x4a008140,
108 .cm_idlest_dpll_per = 0x4a008144,
109 .cm_autoidle_dpll_per = 0x4a008148,
110 .cm_clksel_dpll_per = 0x4a00814c,
111 .cm_div_m2_dpll_per = 0x4a008150,
112 .cm_div_m3_dpll_per = 0x4a008154,
113 .cm_div_h11_dpll_per = 0x4a008158,
114 .cm_div_h12_dpll_per = 0x4a00815c,
115 .cm_div_h14_dpll_per = 0x4a008164,
116 .cm_ssc_deltamstep_dpll_per = 0x4a008168,
117 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
118 .cm_emu_override_dpll_per = 0x4a008170,
119 .cm_clkmode_dpll_usb = 0x4a008180,
120 .cm_idlest_dpll_usb = 0x4a008184,
121 .cm_autoidle_dpll_usb = 0x4a008188,
122 .cm_clksel_dpll_usb = 0x4a00818c,
123 .cm_div_m2_dpll_usb = 0x4a008190,
124 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
125 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
126 .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
127 .cm_clkmode_dpll_unipro = 0x4a0081c0,
128 .cm_idlest_dpll_unipro = 0x4a0081c4,
129 .cm_autoidle_dpll_unipro = 0x4a0081c8,
130 .cm_clksel_dpll_unipro = 0x4a0081cc,
131 .cm_div_m2_dpll_unipro = 0x4a0081d0,
132 .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
133 .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
134
135 /* cm2.core */
136 .cm_coreaon_bandgap_clkctrl = 0x4a008648,
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000[diff] [blame]137 .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]138 .cm_l3_1_clkstctrl = 0x4a008700,
139 .cm_l3_1_dynamicdep = 0x4a008708,
140 .cm_l3_1_l3_1_clkctrl = 0x4a008720,
141 .cm_l3_2_clkstctrl = 0x4a008800,
142 .cm_l3_2_dynamicdep = 0x4a008808,
143 .cm_l3_2_l3_2_clkctrl = 0x4a008820,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]144 .cm_l3_gpmc_clkctrl = 0x4a008828,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]145 .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
146 .cm_mpu_m3_clkstctrl = 0x4a008900,
147 .cm_mpu_m3_staticdep = 0x4a008904,
148 .cm_mpu_m3_dynamicdep = 0x4a008908,
149 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
150 .cm_sdma_clkstctrl = 0x4a008a00,
151 .cm_sdma_staticdep = 0x4a008a04,
152 .cm_sdma_dynamicdep = 0x4a008a08,
153 .cm_sdma_sdma_clkctrl = 0x4a008a20,
154 .cm_memif_clkstctrl = 0x4a008b00,
155 .cm_memif_dmm_clkctrl = 0x4a008b20,
156 .cm_memif_emif_fw_clkctrl = 0x4a008b28,
157 .cm_memif_emif_1_clkctrl = 0x4a008b30,
158 .cm_memif_emif_2_clkctrl = 0x4a008b38,
159 .cm_memif_dll_clkctrl = 0x4a008b40,
160 .cm_memif_emif_h1_clkctrl = 0x4a008b50,
161 .cm_memif_emif_h2_clkctrl = 0x4a008b58,
162 .cm_memif_dll_h_clkctrl = 0x4a008b60,
163 .cm_c2c_clkstctrl = 0x4a008c00,
164 .cm_c2c_staticdep = 0x4a008c04,
165 .cm_c2c_dynamicdep = 0x4a008c08,
166 .cm_c2c_sad2d_clkctrl = 0x4a008c20,
167 .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
168 .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
169 .cm_l4cfg_clkstctrl = 0x4a008d00,
170 .cm_l4cfg_dynamicdep = 0x4a008d08,
171 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
172 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
173 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
174 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
175 .cm_l3instr_clkstctrl = 0x4a008e00,
176 .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
177 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
178 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
179
180 /* cm2.ivahd */
181 .cm_ivahd_clkstctrl = 0x4a008f00,
182 .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
183 .cm_ivahd_sl2_clkctrl = 0x4a008f28,
184
185 /* cm2.cam */
186 .cm_cam_clkstctrl = 0x4a009000,
187 .cm_cam_iss_clkctrl = 0x4a009020,
188 .cm_cam_fdif_clkctrl = 0x4a009028,
189
190 /* cm2.dss */
191 .cm_dss_clkstctrl = 0x4a009100,
192 .cm_dss_dss_clkctrl = 0x4a009120,
193
194 /* cm2.sgx */
195 .cm_sgx_clkstctrl = 0x4a009200,
196 .cm_sgx_sgx_clkctrl = 0x4a009220,
197
198 /* cm2.l3init */
199 .cm_l3init_clkstctrl = 0x4a009300,
200 .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
201 .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
202 .cm_l3init_hsi_clkctrl = 0x4a009338,
203 .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
204 .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
205 .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
206 .cm_l3init_p1500_clkctrl = 0x4a009378,
Roger Quadros8ffcf742013-11-11 16:56:40 +0200[diff] [blame]207 .cm_l3init_sata_clkctrl = 0x4a009388,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]208 .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
209 .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
Roger Quadros8ffcf742013-11-11 16:56:40 +0200[diff] [blame]210 .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]211
212 /* cm2.l4per */
213 .cm_l4per_clkstctrl = 0x4a009400,
214 .cm_l4per_dynamicdep = 0x4a009408,
215 .cm_l4per_adc_clkctrl = 0x4a009420,
216 .cm_l4per_gptimer10_clkctrl = 0x4a009428,
217 .cm_l4per_gptimer11_clkctrl = 0x4a009430,
218 .cm_l4per_gptimer2_clkctrl = 0x4a009438,
219 .cm_l4per_gptimer3_clkctrl = 0x4a009440,
220 .cm_l4per_gptimer4_clkctrl = 0x4a009448,
221 .cm_l4per_gptimer9_clkctrl = 0x4a009450,
222 .cm_l4per_elm_clkctrl = 0x4a009458,
223 .cm_l4per_gpio2_clkctrl = 0x4a009460,
224 .cm_l4per_gpio3_clkctrl = 0x4a009468,
225 .cm_l4per_gpio4_clkctrl = 0x4a009470,
226 .cm_l4per_gpio5_clkctrl = 0x4a009478,
227 .cm_l4per_gpio6_clkctrl = 0x4a009480,
228 .cm_l4per_hdq1w_clkctrl = 0x4a009488,
229 .cm_l4per_hecc1_clkctrl = 0x4a009490,
230 .cm_l4per_hecc2_clkctrl = 0x4a009498,
231 .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
232 .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
233 .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
234 .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
235 .cm_l4per_l4per_clkctrl = 0x4a0094c0,
236 .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
237 .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
238 .cm_l4per_mgate_clkctrl = 0x4a0094e8,
239 .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
240 .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
241 .cm_l4per_mcspi3_clkctrl = 0x4a009500,
242 .cm_l4per_mcspi4_clkctrl = 0x4a009508,
243 .cm_l4per_gpio7_clkctrl = 0x4a009510,
244 .cm_l4per_gpio8_clkctrl = 0x4a009518,
245 .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
246 .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
247 .cm_l4per_msprohg_clkctrl = 0x4a009530,
248 .cm_l4per_slimbus2_clkctrl = 0x4a009538,
249 .cm_l4per_uart1_clkctrl = 0x4a009540,
250 .cm_l4per_uart2_clkctrl = 0x4a009548,
251 .cm_l4per_uart3_clkctrl = 0x4a009550,
252 .cm_l4per_uart4_clkctrl = 0x4a009558,
253 .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
254 .cm_l4per_i2c5_clkctrl = 0x4a009568,
255 .cm_l4per_uart5_clkctrl = 0x4a009570,
256 .cm_l4per_uart6_clkctrl = 0x4a009578,
257 .cm_l4sec_clkstctrl = 0x4a009580,
258 .cm_l4sec_staticdep = 0x4a009584,
259 .cm_l4sec_dynamicdep = 0x4a009588,
260 .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
261 .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
262 .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
263 .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
264 .cm_l4sec_rng_clkctrl = 0x4a0095c0,
265 .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
266 .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
267
268 /* l4 wkup regs */
269 .cm_abe_pll_ref_clksel = 0x4ae0610c,
270 .cm_sys_clksel = 0x4ae06110,
271 .cm_wkup_clkstctrl = 0x4ae07800,
272 .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
273 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
274 .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
275 .cm_wkup_gpio1_clkctrl = 0x4ae07838,
276 .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
277 .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
278 .cm_wkup_synctimer_clkctrl = 0x4ae07850,
279 .cm_wkup_usim_clkctrl = 0x4ae07858,
280 .cm_wkup_sarram_clkctrl = 0x4ae07860,
281 .cm_wkup_keyboard_clkctrl = 0x4ae07878,
282 .cm_wkup_rtc_clkctrl = 0x4ae07880,
283 .cm_wkup_bandgap_clkctrl = 0x4ae07888,
284 .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000[diff] [blame]285 .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]286 .prm_rstctrl = 0x4ae07b00,
287 .prm_rstst = 0x4ae07b04,
Lubomir Popove0a8c992013-05-26 10:03:17 +0000[diff] [blame]288 .prm_rsttime = 0x4ae07b08,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]289 .prm_vc_val_bypass = 0x4ae07ba0,
290 .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
291 .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
Lubomir Popovee28eda2013-05-15 04:41:01 +0000[diff] [blame]292
293 /* SCRM stuff, used by some boards */
294 .scrm_auxclk0 = 0x4ae0a310,
295 .scrm_auxclk1 = 0x4ae0a314,
SRICHARAN R01b753f2013-02-04 04:22:00 +0000[diff] [blame]296};
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000[diff] [blame]297
298struct omap_sys_ctrl_regs const omap5_ctrl = {
299 .control_status = 0x4A002134,
Paul Kocialkowski9fd54012015-08-27 19:37:11 +0200[diff] [blame]300 .control_std_fuse_die_id_0 = 0x4A002200,
301 .control_std_fuse_die_id_1 = 0x4A002208,
302 .control_std_fuse_die_id_2 = 0x4A00220C,
303 .control_std_fuse_die_id_3 = 0x4A002210,
Dan Murphyd861a332013-08-26 08:54:50 -0500[diff] [blame]304 .control_phy_power_usb = 0x4A002370,
Roger Quadros8ffcf742013-11-11 16:56:40 +0200[diff] [blame]305 .control_phy_power_sata = 0x4A002374,
Lokesh Vutla9239f5b2013-05-30 02:54:30 +0000[diff] [blame]306 .control_padconf_core_base = 0x4A002800,
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000[diff] [blame]307 .control_paconf_global = 0x4A002DA0,
308 .control_paconf_mode = 0x4A002DA4,
309 .control_smart1io_padconf_0 = 0x4A002DA8,
310 .control_smart1io_padconf_1 = 0x4A002DAC,
311 .control_smart1io_padconf_2 = 0x4A002DB0,
312 .control_smart2io_padconf_0 = 0x4A002DB4,
313 .control_smart2io_padconf_1 = 0x4A002DB8,
314 .control_smart2io_padconf_2 = 0x4A002DBC,
315 .control_smart3io_padconf_0 = 0x4A002DC0,
316 .control_smart3io_padconf_1 = 0x4A002DC4,
317 .control_pbias = 0x4A002E00,
318 .control_i2c_0 = 0x4A002E04,
319 .control_camera_rx = 0x4A002E08,
320 .control_hdmi_tx_phy = 0x4A002E0C,
321 .control_uniportm = 0x4A002E10,
322 .control_dsiphy = 0x4A002E14,
323 .control_mcbsplp = 0x4A002E18,
324 .control_usb2phycore = 0x4A002E1C,
325 .control_hdmi_1 = 0x4A002E20,
326 .control_hsi = 0x4A002E24,
327 .control_ddr3ch1_0 = 0x4A002E30,
328 .control_ddr3ch2_0 = 0x4A002E34,
329 .control_ddrch1_0 = 0x4A002E38,
330 .control_ddrch1_1 = 0x4A002E3C,
331 .control_ddrch2_0 = 0x4A002E40,
332 .control_ddrch2_1 = 0x4A002E44,
333 .control_lpddr2ch1_0 = 0x4A002E48,
334 .control_lpddr2ch1_1 = 0x4A002E4C,
335 .control_ddrio_0 = 0x4A002E50,
336 .control_ddrio_1 = 0x4A002E54,
337 .control_ddrio_2 = 0x4A002E58,
338 .control_hyst_1 = 0x4A002E5C,
339 .control_usbb_hsic_control = 0x4A002E60,
340 .control_c2c = 0x4A002E64,
341 .control_core_control_spare_rw = 0x4A002E68,
342 .control_core_control_spare_r = 0x4A002E6C,
343 .control_core_control_spare_r_c0 = 0x4A002E70,
344 .control_srcomp_north_side = 0x4A002E74,
345 .control_srcomp_south_side = 0x4A002E78,
346 .control_srcomp_east_side = 0x4A002E7C,
347 .control_srcomp_west_side = 0x4A002E80,
348 .control_srcomp_code_latch = 0x4A002E84,
349 .control_port_emif1_sdram_config = 0x4AE0C110,
350 .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
351 .control_port_emif2_sdram_config = 0x4AE0C118,
352 .control_emif1_sdram_config_ext = 0x4AE0C144,
353 .control_emif2_sdram_config_ext = 0x4AE0C148,
Andrii Tseglytskyie69c5852013-05-20 22:42:09 +0000[diff] [blame]354 .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318,
Nishanth Menona8180972016-04-21 14:34:24 -0500[diff] [blame]355 .control_wkup_ldovbb_mm_voltage_ctrl = 0x4AE0C314,
Lokesh Vutla9239f5b2013-05-30 02:54:30 +0000[diff] [blame]356 .control_padconf_wkup_base = 0x4AE0C800,
Lokesh Vutlac43c8332013-02-04 04:22:04 +0000[diff] [blame]357 .control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
358 .control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
359 .control_padconf_mode = 0x4AE0CDA8,
360 .control_xtal_oscillator = 0x4AE0CDAC,
361 .control_i2c_2 = 0x4AE0CDB0,
362 .control_ckobuffer = 0x4AE0CDB4,
363 .control_wkup_control_spare_rw = 0x4AE0CDB8,
364 .control_wkup_control_spare_r = 0x4AE0CDBC,
365 .control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
366 .control_srcomp_east_side_wkup = 0x4AE0CDC4,
367 .control_efuse_1 = 0x4AE0CDC8,
368 .control_efuse_2 = 0x4AE0CDCC,
369 .control_efuse_3 = 0x4AE0CDD0,
370 .control_efuse_4 = 0x4AE0CDD4,
371 .control_efuse_5 = 0x4AE0CDD8,
372 .control_efuse_6 = 0x4AE0CDDC,
373 .control_efuse_7 = 0x4AE0CDE0,
374 .control_efuse_8 = 0x4AE0CDE4,
375 .control_efuse_9 = 0x4AE0CDE8,
376 .control_efuse_10 = 0x4AE0CDEC,
377 .control_efuse_11 = 0x4AE0CDF0,
378 .control_efuse_12 = 0x4AE0CDF4,
379 .control_efuse_13 = 0x4AE0CDF8,
380};
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]381
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]382struct omap_sys_ctrl_regs const dra7xx_ctrl = {
383 .control_status = 0x4A002134,
Felipe Balbi113d7e82014-11-06 08:28:44 -0600[diff] [blame]384 .control_phy_power_usb = 0x4A002370,
Roger Quadros5afded62013-11-11 16:56:43 +0200[diff] [blame]385 .control_phy_power_sata = 0x4A002374,
Lokesh Vutlaeda6fbc2015-06-04 16:42:36 +0530[diff] [blame]386 .ctrl_core_sma_sw_0 = 0x4A0023FC,
Nishanth Menon76cff2b2015-08-13 09:51:00 -0500[diff] [blame]387 .ctrl_core_sma_sw_1 = 0x4A002534,
Mugunthan V Nb1e26e32013-07-08 16:04:41 +0530[diff] [blame]388 .control_core_mac_id_0_lo = 0x4A002514,
389 .control_core_mac_id_0_hi = 0x4A002518,
390 .control_core_mac_id_1_lo = 0x4A00251C,
391 .control_core_mac_id_1_hi = 0x4A002520,
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]392 .control_core_mmr_lock1 = 0x4A002540,
393 .control_core_mmr_lock2 = 0x4A002544,
394 .control_core_mmr_lock3 = 0x4A002548,
395 .control_core_mmr_lock4 = 0x4A00254C,
396 .control_core_mmr_lock5 = 0x4A002550,
397 .control_core_control_io1 = 0x4A002554,
398 .control_core_control_io2 = 0x4A002558,
399 .control_paconf_global = 0x4A002DA0,
400 .control_paconf_mode = 0x4A002DA4,
401 .control_smart1io_padconf_0 = 0x4A002DA8,
402 .control_smart1io_padconf_1 = 0x4A002DAC,
403 .control_smart1io_padconf_2 = 0x4A002DB0,
404 .control_smart2io_padconf_0 = 0x4A002DB4,
405 .control_smart2io_padconf_1 = 0x4A002DB8,
406 .control_smart2io_padconf_2 = 0x4A002DBC,
407 .control_smart3io_padconf_0 = 0x4A002DC0,
408 .control_smart3io_padconf_1 = 0x4A002DC4,
409 .control_pbias = 0x4A002E00,
410 .control_i2c_0 = 0x4A002E04,
411 .control_camera_rx = 0x4A002E08,
412 .control_hdmi_tx_phy = 0x4A002E0C,
413 .control_uniportm = 0x4A002E10,
414 .control_dsiphy = 0x4A002E14,
415 .control_mcbsplp = 0x4A002E18,
416 .control_usb2phycore = 0x4A002E1C,
417 .control_hdmi_1 = 0x4A002E20,
418 .control_hsi = 0x4A002E24,
419 .control_ddr3ch1_0 = 0x4A002E30,
420 .control_ddr3ch2_0 = 0x4A002E34,
421 .control_ddrch1_0 = 0x4A002E38,
422 .control_ddrch1_1 = 0x4A002E3C,
423 .control_ddrch2_0 = 0x4A002E40,
424 .control_ddrch2_1 = 0x4A002E44,
425 .control_lpddr2ch1_0 = 0x4A002E48,
426 .control_lpddr2ch1_1 = 0x4A002E4C,
427 .control_ddrio_0 = 0x4A002E50,
428 .control_ddrio_1 = 0x4A002E54,
429 .control_ddrio_2 = 0x4A002E58,
430 .control_hyst_1 = 0x4A002E5C,
431 .control_usbb_hsic_control = 0x4A002E60,
432 .control_c2c = 0x4A002E64,
433 .control_core_control_spare_rw = 0x4A002E68,
434 .control_core_control_spare_r = 0x4A002E6C,
435 .control_core_control_spare_r_c0 = 0x4A002E70,
436 .control_srcomp_north_side = 0x4A002E74,
437 .control_srcomp_south_side = 0x4A002E78,
438 .control_srcomp_east_side = 0x4A002E7C,
439 .control_srcomp_west_side = 0x4A002E80,
440 .control_srcomp_code_latch = 0x4A002E84,
Sricharan R92b04822013-05-30 03:19:39 +0000[diff] [blame]441 .control_ddr_control_ext_0 = 0x4A002E88,
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]442 .control_padconf_core_base = 0x4A003400,
443 .control_port_emif1_sdram_config = 0x4AE0C110,
444 .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
445 .control_port_emif2_sdram_config = 0x4AE0C118,
446 .control_emif1_sdram_config_ext = 0x4AE0C144,
447 .control_emif2_sdram_config_ext = 0x4AE0C148,
Nishanth Menon194dd742014-01-14 12:27:29 -0600[diff] [blame]448 .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
Nishanth Menone52e3342016-04-21 14:34:25 -0500[diff] [blame]449 .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470,
450 .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C,
451 .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154,
Dileep Kattaf12467d2015-03-25 04:04:51 +0530[diff] [blame]452 .control_std_fuse_die_id_0 = 0x4AE0C200,
453 .control_std_fuse_die_id_1 = 0x4AE0C208,
454 .control_std_fuse_die_id_2 = 0x4AE0C20C,
455 .control_std_fuse_die_id_3 = 0x4AE0C210,
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]456 .control_padconf_mode = 0x4AE0C5A0,
457 .control_xtal_oscillator = 0x4AE0C5A4,
458 .control_i2c_2 = 0x4AE0C5A8,
459 .control_ckobuffer = 0x4AE0C5AC,
460 .control_wkup_control_spare_rw = 0x4AE0C5B0,
461 .control_wkup_control_spare_r = 0x4AE0C5B4,
462 .control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
463 .control_srcomp_east_side_wkup = 0x4AE0C5BC,
Lokesh Vutla02847fc2014-05-15 11:08:42 +0530[diff] [blame]464 .control_efuse_1 = 0x4AE0C5C8,
465 .control_efuse_2 = 0x4AE0C5CC,
466 .control_efuse_3 = 0x4AE0C5D0,
467 .control_efuse_4 = 0x4AE0C5D4,
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]468 .control_efuse_13 = 0x4AE0C5F0,
Lokesh Vutlaeda6fbc2015-06-04 16:42:36 +0530[diff] [blame]469 .iodelay_config_base = 0x4844A000,
Lokesh Vutla8b12f172013-02-12 21:29:06 +0000[diff] [blame]470};
471
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]472struct prcm_regs const omap5_es2_prcm = {
473 /* cm1.ckgen */
474 .cm_clksel_core = 0x4a004100,
475 .cm_clksel_abe = 0x4a004108,
476 .cm_dll_ctrl = 0x4a004110,
477 .cm_clkmode_dpll_core = 0x4a004120,
478 .cm_idlest_dpll_core = 0x4a004124,
479 .cm_autoidle_dpll_core = 0x4a004128,
480 .cm_clksel_dpll_core = 0x4a00412c,
481 .cm_div_m2_dpll_core = 0x4a004130,
482 .cm_div_m3_dpll_core = 0x4a004134,
483 .cm_div_h11_dpll_core = 0x4a004138,
484 .cm_div_h12_dpll_core = 0x4a00413c,
485 .cm_div_h13_dpll_core = 0x4a004140,
486 .cm_div_h14_dpll_core = 0x4a004144,
487 .cm_ssc_deltamstep_dpll_core = 0x4a004148,
488 .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
489 .cm_div_h21_dpll_core = 0x4a004150,
490 .cm_div_h22_dpllcore = 0x4a004154,
491 .cm_div_h23_dpll_core = 0x4a004158,
492 .cm_div_h24_dpll_core = 0x4a00415c,
493 .cm_clkmode_dpll_mpu = 0x4a004160,
494 .cm_idlest_dpll_mpu = 0x4a004164,
495 .cm_autoidle_dpll_mpu = 0x4a004168,
496 .cm_clksel_dpll_mpu = 0x4a00416c,
497 .cm_div_m2_dpll_mpu = 0x4a004170,
498 .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
499 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
500 .cm_bypclk_dpll_mpu = 0x4a00419c,
501 .cm_clkmode_dpll_iva = 0x4a0041a0,
502 .cm_idlest_dpll_iva = 0x4a0041a4,
503 .cm_autoidle_dpll_iva = 0x4a0041a8,
504 .cm_clksel_dpll_iva = 0x4a0041ac,
505 .cm_div_h11_dpll_iva = 0x4a0041b8,
506 .cm_div_h12_dpll_iva = 0x4a0041bc,
507 .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
508 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
509 .cm_bypclk_dpll_iva = 0x4a0041dc,
510 .cm_clkmode_dpll_abe = 0x4a0041e0,
511 .cm_idlest_dpll_abe = 0x4a0041e4,
512 .cm_autoidle_dpll_abe = 0x4a0041e8,
513 .cm_clksel_dpll_abe = 0x4a0041ec,
514 .cm_div_m2_dpll_abe = 0x4a0041f0,
515 .cm_div_m3_dpll_abe = 0x4a0041f4,
516 .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
517 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
518 .cm_clkmode_dpll_ddrphy = 0x4a004220,
519 .cm_idlest_dpll_ddrphy = 0x4a004224,
520 .cm_autoidle_dpll_ddrphy = 0x4a004228,
521 .cm_clksel_dpll_ddrphy = 0x4a00422c,
522 .cm_div_m2_dpll_ddrphy = 0x4a004230,
523 .cm_div_h11_dpll_ddrphy = 0x4a004238,
524 .cm_div_h12_dpll_ddrphy = 0x4a00423c,
525 .cm_div_h13_dpll_ddrphy = 0x4a004240,
526 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
527 .cm_shadow_freq_config1 = 0x4a004260,
528 .cm_mpu_mpu_clkctrl = 0x4a004320,
529
530 /* cm1.dsp */
531 .cm_dsp_clkstctrl = 0x4a004400,
532 .cm_dsp_dsp_clkctrl = 0x4a004420,
533
534 /* cm1.abe */
535 .cm1_abe_clkstctrl = 0x4a004500,
536 .cm1_abe_l4abe_clkctrl = 0x4a004520,
537 .cm1_abe_aess_clkctrl = 0x4a004528,
538 .cm1_abe_pdm_clkctrl = 0x4a004530,
539 .cm1_abe_dmic_clkctrl = 0x4a004538,
540 .cm1_abe_mcasp_clkctrl = 0x4a004540,
541 .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
542 .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
543 .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
544 .cm1_abe_slimbus_clkctrl = 0x4a004560,
545 .cm1_abe_timer5_clkctrl = 0x4a004568,
546 .cm1_abe_timer6_clkctrl = 0x4a004570,
547 .cm1_abe_timer7_clkctrl = 0x4a004578,
548 .cm1_abe_timer8_clkctrl = 0x4a004580,
549 .cm1_abe_wdt3_clkctrl = 0x4a004588,
550
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]551 /* cm2.ckgen */
552 .cm_clksel_mpu_m3_iss_root = 0x4a008100,
553 .cm_clksel_usb_60mhz = 0x4a008104,
554 .cm_scale_fclk = 0x4a008108,
555 .cm_core_dvfs_perf1 = 0x4a008110,
556 .cm_core_dvfs_perf2 = 0x4a008114,
557 .cm_core_dvfs_perf3 = 0x4a008118,
558 .cm_core_dvfs_perf4 = 0x4a00811c,
559 .cm_core_dvfs_current = 0x4a008124,
560 .cm_iva_dvfs_perf_tesla = 0x4a008128,
561 .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
562 .cm_iva_dvfs_perf_abe = 0x4a008130,
563 .cm_iva_dvfs_current = 0x4a008138,
564 .cm_clkmode_dpll_per = 0x4a008140,
565 .cm_idlest_dpll_per = 0x4a008144,
566 .cm_autoidle_dpll_per = 0x4a008148,
567 .cm_clksel_dpll_per = 0x4a00814c,
568 .cm_div_m2_dpll_per = 0x4a008150,
569 .cm_div_m3_dpll_per = 0x4a008154,
570 .cm_div_h11_dpll_per = 0x4a008158,
571 .cm_div_h12_dpll_per = 0x4a00815c,
572 .cm_div_h13_dpll_per = 0x4a008160,
573 .cm_div_h14_dpll_per = 0x4a008164,
574 .cm_ssc_deltamstep_dpll_per = 0x4a008168,
575 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
576 .cm_emu_override_dpll_per = 0x4a008170,
577 .cm_clkmode_dpll_usb = 0x4a008180,
578 .cm_idlest_dpll_usb = 0x4a008184,
579 .cm_autoidle_dpll_usb = 0x4a008188,
580 .cm_clksel_dpll_usb = 0x4a00818c,
581 .cm_div_m2_dpll_usb = 0x4a008190,
582 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
583 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
584 .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
585 .cm_clkmode_dpll_unipro = 0x4a0081c0,
586 .cm_idlest_dpll_unipro = 0x4a0081c4,
587 .cm_autoidle_dpll_unipro = 0x4a0081c8,
588 .cm_clksel_dpll_unipro = 0x4a0081cc,
589 .cm_div_m2_dpll_unipro = 0x4a0081d0,
590 .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
591 .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
Kishon Vijay Abraham Id3cfcb32015-02-23 18:39:44 +0530[diff] [blame]592 .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]593 .cm_coreaon_bandgap_clkctrl = 0x4a008648,
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000[diff] [blame]594 .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]595
596 /* cm2.core */
597 .cm_l3_1_clkstctrl = 0x4a008700,
598 .cm_l3_1_dynamicdep = 0x4a008708,
599 .cm_l3_1_l3_1_clkctrl = 0x4a008720,
600 .cm_l3_2_clkstctrl = 0x4a008800,
601 .cm_l3_2_dynamicdep = 0x4a008808,
602 .cm_l3_2_l3_2_clkctrl = 0x4a008820,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]603 .cm_l3_gpmc_clkctrl = 0x4a008828,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]604 .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
605 .cm_mpu_m3_clkstctrl = 0x4a008900,
606 .cm_mpu_m3_staticdep = 0x4a008904,
607 .cm_mpu_m3_dynamicdep = 0x4a008908,
608 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
609 .cm_sdma_clkstctrl = 0x4a008a00,
610 .cm_sdma_staticdep = 0x4a008a04,
611 .cm_sdma_dynamicdep = 0x4a008a08,
612 .cm_sdma_sdma_clkctrl = 0x4a008a20,
613 .cm_memif_clkstctrl = 0x4a008b00,
614 .cm_memif_dmm_clkctrl = 0x4a008b20,
615 .cm_memif_emif_fw_clkctrl = 0x4a008b28,
616 .cm_memif_emif_1_clkctrl = 0x4a008b30,
617 .cm_memif_emif_2_clkctrl = 0x4a008b38,
618 .cm_memif_dll_clkctrl = 0x4a008b40,
619 .cm_memif_emif_h1_clkctrl = 0x4a008b50,
620 .cm_memif_emif_h2_clkctrl = 0x4a008b58,
621 .cm_memif_dll_h_clkctrl = 0x4a008b60,
622 .cm_c2c_clkstctrl = 0x4a008c00,
623 .cm_c2c_staticdep = 0x4a008c04,
624 .cm_c2c_dynamicdep = 0x4a008c08,
625 .cm_c2c_sad2d_clkctrl = 0x4a008c20,
626 .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
627 .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
628 .cm_l4cfg_clkstctrl = 0x4a008d00,
629 .cm_l4cfg_dynamicdep = 0x4a008d08,
630 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
631 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
632 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
633 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
634 .cm_l3instr_clkstctrl = 0x4a008e00,
635 .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
636 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
637 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
638 .cm_l4per_clkstctrl = 0x4a009000,
639 .cm_l4per_dynamicdep = 0x4a009008,
640 .cm_l4per_adc_clkctrl = 0x4a009020,
641 .cm_l4per_gptimer10_clkctrl = 0x4a009028,
642 .cm_l4per_gptimer11_clkctrl = 0x4a009030,
643 .cm_l4per_gptimer2_clkctrl = 0x4a009038,
644 .cm_l4per_gptimer3_clkctrl = 0x4a009040,
645 .cm_l4per_gptimer4_clkctrl = 0x4a009048,
646 .cm_l4per_gptimer9_clkctrl = 0x4a009050,
647 .cm_l4per_elm_clkctrl = 0x4a009058,
648 .cm_l4per_gpio2_clkctrl = 0x4a009060,
649 .cm_l4per_gpio3_clkctrl = 0x4a009068,
650 .cm_l4per_gpio4_clkctrl = 0x4a009070,
651 .cm_l4per_gpio5_clkctrl = 0x4a009078,
652 .cm_l4per_gpio6_clkctrl = 0x4a009080,
653 .cm_l4per_hdq1w_clkctrl = 0x4a009088,
654 .cm_l4per_hecc1_clkctrl = 0x4a009090,
655 .cm_l4per_hecc2_clkctrl = 0x4a009098,
656 .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
657 .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
658 .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
659 .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
660 .cm_l4per_l4per_clkctrl = 0x4a0090c0,
661 .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
662 .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
663 .cm_l4per_mgate_clkctrl = 0x4a0090e8,
664 .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
665 .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
666 .cm_l4per_mcspi3_clkctrl = 0x4a009100,
667 .cm_l4per_mcspi4_clkctrl = 0x4a009108,
668 .cm_l4per_gpio7_clkctrl = 0x4a009110,
669 .cm_l4per_gpio8_clkctrl = 0x4a009118,
670 .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
671 .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
672 .cm_l4per_msprohg_clkctrl = 0x4a009130,
673 .cm_l4per_slimbus2_clkctrl = 0x4a009138,
674 .cm_l4per_uart1_clkctrl = 0x4a009140,
675 .cm_l4per_uart2_clkctrl = 0x4a009148,
676 .cm_l4per_uart3_clkctrl = 0x4a009150,
677 .cm_l4per_uart4_clkctrl = 0x4a009158,
678 .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
679 .cm_l4per_i2c5_clkctrl = 0x4a009168,
680 .cm_l4per_uart5_clkctrl = 0x4a009170,
681 .cm_l4per_uart6_clkctrl = 0x4a009178,
682 .cm_l4sec_clkstctrl = 0x4a009180,
683 .cm_l4sec_staticdep = 0x4a009184,
684 .cm_l4sec_dynamicdep = 0x4a009188,
685 .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
686 .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
687 .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
688 .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
689 .cm_l4sec_rng_clkctrl = 0x4a0091c0,
690 .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
691 .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
692
693 /* cm2.ivahd */
694 .cm_ivahd_clkstctrl = 0x4a009200,
695 .cm_ivahd_ivahd_clkctrl = 0x4a009220,
696 .cm_ivahd_sl2_clkctrl = 0x4a009228,
697
698 /* cm2.cam */
699 .cm_cam_clkstctrl = 0x4a009300,
700 .cm_cam_iss_clkctrl = 0x4a009320,
701 .cm_cam_fdif_clkctrl = 0x4a009328,
702
703 /* cm2.dss */
704 .cm_dss_clkstctrl = 0x4a009400,
705 .cm_dss_dss_clkctrl = 0x4a009420,
706
707 /* cm2.sgx */
708 .cm_sgx_clkstctrl = 0x4a009500,
709 .cm_sgx_sgx_clkctrl = 0x4a009520,
710
711 /* cm2.l3init */
712 .cm_l3init_clkstctrl = 0x4a009600,
713
714 /* cm2.l3init */
715 .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
716 .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
717 .cm_l3init_hsi_clkctrl = 0x4a009638,
718 .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
719 .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
720 .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
721 .cm_l3init_p1500_clkctrl = 0x4a009678,
Roger Quadros8ffcf742013-11-11 16:56:40 +0200[diff] [blame]722 .cm_l3init_sata_clkctrl = 0x4a009688,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]723 .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
724 .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
Dan Murphyd861a332013-08-26 08:54:50 -0500[diff] [blame]725 .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
Kishon Vijay Abraham Id3cfcb32015-02-23 18:39:44 +0530[diff] [blame]726 .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]727
Andrii Tseglytskyie69c5852013-05-20 22:42:09 +0000[diff] [blame]728 /* prm irqstatus regs */
Nishanth Menona8180972016-04-21 14:34:24 -0500[diff] [blame]729 .prm_irqstatus_mpu = 0x4ae06010,
Andrii Tseglytskyie69c5852013-05-20 22:42:09 +0000[diff] [blame]730 .prm_irqstatus_mpu_2 = 0x4ae06014,
731
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]732 /* l4 wkup regs */
733 .cm_abe_pll_ref_clksel = 0x4ae0610c,
734 .cm_sys_clksel = 0x4ae06110,
735 .cm_wkup_clkstctrl = 0x4ae07900,
736 .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
737 .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
738 .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
739 .cm_wkup_gpio1_clkctrl = 0x4ae07938,
740 .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
741 .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
742 .cm_wkup_synctimer_clkctrl = 0x4ae07950,
743 .cm_wkup_usim_clkctrl = 0x4ae07958,
744 .cm_wkup_sarram_clkctrl = 0x4ae07960,
745 .cm_wkup_keyboard_clkctrl = 0x4ae07978,
746 .cm_wkup_rtc_clkctrl = 0x4ae07980,
747 .cm_wkup_bandgap_clkctrl = 0x4ae07988,
748 .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
Lokesh Vutlad4d986e2013-02-12 01:33:45 +0000[diff] [blame]749 .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]750 .prm_rstctrl = 0x4ae07c00,
751 .prm_rstst = 0x4ae07c04,
Lokesh Vutla0b1b60c2013-04-17 20:49:40 +0000[diff] [blame]752 .prm_rsttime = 0x4ae07c08,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]753 .prm_vc_val_bypass = 0x4ae07ca0,
754 .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
755 .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
756
Andrii Tseglytskyie69c5852013-05-20 22:42:09 +0000[diff] [blame]757 .prm_abbldo_mpu_setup = 0x4ae07cdc,
758 .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
Nishanth Menona8180972016-04-21 14:34:24 -0500[diff] [blame]759 .prm_abbldo_mm_setup = 0x4ae07ce4,
760 .prm_abbldo_mm_ctrl = 0x4ae07ce8,
Lubomir Popovee28eda2013-05-15 04:41:01 +0000[diff] [blame]761
762 /* SCRM stuff, used by some boards */
763 .scrm_auxclk0 = 0x4ae0a310,
764 .scrm_auxclk1 = 0x4ae0a314,
SRICHARAN Rafc2f9d2013-02-12 01:33:42 +0000[diff] [blame]765};
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]766
767struct prcm_regs const dra7xx_prcm = {
768 /* cm1.ckgen */
769 .cm_clksel_core = 0x4a005100,
770 .cm_clksel_abe = 0x4a005108,
771 .cm_dll_ctrl = 0x4a005110,
772 .cm_clkmode_dpll_core = 0x4a005120,
773 .cm_idlest_dpll_core = 0x4a005124,
774 .cm_autoidle_dpll_core = 0x4a005128,
775 .cm_clksel_dpll_core = 0x4a00512c,
776 .cm_div_m2_dpll_core = 0x4a005130,
777 .cm_div_m3_dpll_core = 0x4a005134,
778 .cm_div_h11_dpll_core = 0x4a005138,
779 .cm_div_h12_dpll_core = 0x4a00513c,
780 .cm_div_h13_dpll_core = 0x4a005140,
781 .cm_div_h14_dpll_core = 0x4a005144,
782 .cm_ssc_deltamstep_dpll_core = 0x4a005148,
783 .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
784 .cm_div_h21_dpll_core = 0x4a005150,
785 .cm_div_h22_dpllcore = 0x4a005154,
786 .cm_div_h23_dpll_core = 0x4a005158,
787 .cm_div_h24_dpll_core = 0x4a00515c,
788 .cm_clkmode_dpll_mpu = 0x4a005160,
789 .cm_idlest_dpll_mpu = 0x4a005164,
790 .cm_autoidle_dpll_mpu = 0x4a005168,
791 .cm_clksel_dpll_mpu = 0x4a00516c,
792 .cm_div_m2_dpll_mpu = 0x4a005170,
793 .cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
794 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
795 .cm_bypclk_dpll_mpu = 0x4a00519c,
796 .cm_clkmode_dpll_iva = 0x4a0051a0,
797 .cm_idlest_dpll_iva = 0x4a0051a4,
798 .cm_autoidle_dpll_iva = 0x4a0051a8,
799 .cm_clksel_dpll_iva = 0x4a0051ac,
800 .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
801 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
802 .cm_bypclk_dpll_iva = 0x4a0051dc,
803 .cm_clkmode_dpll_abe = 0x4a0051e0,
804 .cm_idlest_dpll_abe = 0x4a0051e4,
805 .cm_autoidle_dpll_abe = 0x4a0051e8,
806 .cm_clksel_dpll_abe = 0x4a0051ec,
807 .cm_div_m2_dpll_abe = 0x4a0051f0,
808 .cm_div_m3_dpll_abe = 0x4a0051f4,
809 .cm_ssc_deltamstep_dpll_abe = 0x4a005208,
810 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
811 .cm_clkmode_dpll_ddrphy = 0x4a005210,
812 .cm_idlest_dpll_ddrphy = 0x4a005214,
813 .cm_autoidle_dpll_ddrphy = 0x4a005218,
814 .cm_clksel_dpll_ddrphy = 0x4a00521c,
815 .cm_div_m2_dpll_ddrphy = 0x4a005220,
816 .cm_div_h11_dpll_ddrphy = 0x4a005228,
817 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
818 .cm_clkmode_dpll_dsp = 0x4a005234,
819 .cm_shadow_freq_config1 = 0x4a005260,
Lokesh Vutla65e9d562013-07-08 16:04:39 +0530[diff] [blame]820 .cm_clkmode_dpll_gmac = 0x4a0052a8,
Kishon Vijay Abraham Id3cfcb32015-02-23 18:39:44 +0530[diff] [blame]821 .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
822 .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
Roger Quadros35997742016-05-23 17:37:49 +0300[diff] [blame]823 .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
Kishon Vijay Abraham I7beaf8b2015-08-10 16:52:55 +0530[diff] [blame]824 .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]825
826 /* cm1.mpu */
827 .cm_mpu_mpu_clkctrl = 0x4a005320,
828
829 /* cm1.dsp */
830 .cm_dsp_clkstctrl = 0x4a005400,
831 .cm_dsp_dsp_clkctrl = 0x4a005420,
832
Lokesh Vutla37be54f2015-06-05 15:19:21 +0530[diff] [blame]833 /* cm IPU */
834 .cm_ipu_clkstctrl = 0x4a005540,
835 .cm_ipu_i2c5_clkctrl = 0x4a005578,
836
Nishanth Menon194dd742014-01-14 12:27:29 -0600[diff] [blame]837 /* prm irqstatus regs */
Nishanth Menone52e3342016-04-21 14:34:25 -0500[diff] [blame]838 .prm_irqstatus_mpu = 0x4ae06010,
Nishanth Menon194dd742014-01-14 12:27:29 -0600[diff] [blame]839 .prm_irqstatus_mpu_2 = 0x4ae06014,
840
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]841 /* cm2.ckgen */
842 .cm_clksel_usb_60mhz = 0x4a008104,
843 .cm_clkmode_dpll_per = 0x4a008140,
844 .cm_idlest_dpll_per = 0x4a008144,
845 .cm_autoidle_dpll_per = 0x4a008148,
846 .cm_clksel_dpll_per = 0x4a00814c,
847 .cm_div_m2_dpll_per = 0x4a008150,
848 .cm_div_m3_dpll_per = 0x4a008154,
849 .cm_div_h11_dpll_per = 0x4a008158,
850 .cm_div_h12_dpll_per = 0x4a00815c,
851 .cm_div_h13_dpll_per = 0x4a008160,
852 .cm_div_h14_dpll_per = 0x4a008164,
853 .cm_ssc_deltamstep_dpll_per = 0x4a008168,
854 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
855 .cm_clkmode_dpll_usb = 0x4a008180,
856 .cm_idlest_dpll_usb = 0x4a008184,
857 .cm_autoidle_dpll_usb = 0x4a008188,
858 .cm_clksel_dpll_usb = 0x4a00818c,
859 .cm_div_m2_dpll_usb = 0x4a008190,
860 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
861 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
862 .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
863 .cm_clkmode_dpll_pcie_ref = 0x4a008200,
864 .cm_clkmode_apll_pcie = 0x4a00821c,
865 .cm_idlest_apll_pcie = 0x4a008220,
866 .cm_div_m2_apll_pcie = 0x4a008224,
867 .cm_clkvcoldo_apll_pcie = 0x4a008228,
868
869 /* cm2.core */
870 .cm_l3_1_clkstctrl = 0x4a008700,
871 .cm_l3_1_dynamicdep = 0x4a008708,
872 .cm_l3_1_l3_1_clkctrl = 0x4a008720,
873 .cm_l3_gpmc_clkctrl = 0x4a008728,
874 .cm_mpu_m3_clkstctrl = 0x4a008900,
875 .cm_mpu_m3_staticdep = 0x4a008904,
876 .cm_mpu_m3_dynamicdep = 0x4a008908,
877 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
878 .cm_sdma_clkstctrl = 0x4a008a00,
879 .cm_sdma_staticdep = 0x4a008a04,
880 .cm_sdma_dynamicdep = 0x4a008a08,
881 .cm_sdma_sdma_clkctrl = 0x4a008a20,
882 .cm_memif_clkstctrl = 0x4a008b00,
883 .cm_memif_dmm_clkctrl = 0x4a008b20,
884 .cm_memif_emif_fw_clkctrl = 0x4a008b28,
885 .cm_memif_emif_1_clkctrl = 0x4a008b30,
886 .cm_memif_emif_2_clkctrl = 0x4a008b38,
887 .cm_memif_dll_clkctrl = 0x4a008b40,
888 .cm_l4cfg_clkstctrl = 0x4a008d00,
889 .cm_l4cfg_dynamicdep = 0x4a008d08,
890 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
891 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
892 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
893 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
894 .cm_l3instr_clkstctrl = 0x4a008e00,
895 .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
896 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
897 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
898
899 /* cm2.ivahd */
900 .cm_ivahd_clkstctrl = 0x4a008f00,
901 .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
902 .cm_ivahd_sl2_clkctrl = 0x4a008f28,
903
904 /* cm2.cam */
905 .cm_cam_clkstctrl = 0x4a009000,
906 .cm_cam_vip1_clkctrl = 0x4a009020,
907 .cm_cam_vip2_clkctrl = 0x4a009028,
908 .cm_cam_vip3_clkctrl = 0x4a009030,
909 .cm_cam_lvdsrx_clkctrl = 0x4a009038,
910 .cm_cam_csi1_clkctrl = 0x4a009040,
911 .cm_cam_csi2_clkctrl = 0x4a009048,
912
913 /* cm2.dss */
914 .cm_dss_clkstctrl = 0x4a009100,
915 .cm_dss_dss_clkctrl = 0x4a009120,
916
917 /* cm2.sgx */
918 .cm_sgx_clkstctrl = 0x4a009200,
919 .cm_sgx_sgx_clkctrl = 0x4a009220,
920
921 /* cm2.l3init */
922 .cm_l3init_clkstctrl = 0x4a009300,
923
924 /* cm2.l3init */
925 .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
926 .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
927 .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
928 .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
929 .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
Roger Quadros5afded62013-11-11 16:56:43 +0200[diff] [blame]930 .cm_l3init_sata_clkctrl = 0x4a009388,
Mugunthan V Nf986d972013-07-08 16:04:40 +0530[diff] [blame]931 .cm_gmac_clkstctrl = 0x4a0093c0,
932 .cm_gmac_gmac_clkctrl = 0x4a0093d0,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]933 .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
Roger Quadros5afded62013-11-11 16:56:43 +0200[diff] [blame]934 .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
Kishon Vijay Abraham Id3cfcb32015-02-23 18:39:44 +0530[diff] [blame]935 .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0,
Kishon Vijay Abraham I7beaf8b2015-08-10 16:52:55 +0530[diff] [blame]936 .cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]937
938 /* cm2.l4per */
939 .cm_l4per_clkstctrl = 0x4a009700,
940 .cm_l4per_dynamicdep = 0x4a009708,
941 .cm_l4per_gptimer10_clkctrl = 0x4a009728,
942 .cm_l4per_gptimer11_clkctrl = 0x4a009730,
943 .cm_l4per_gptimer2_clkctrl = 0x4a009738,
944 .cm_l4per_gptimer3_clkctrl = 0x4a009740,
945 .cm_l4per_gptimer4_clkctrl = 0x4a009748,
946 .cm_l4per_gptimer9_clkctrl = 0x4a009750,
947 .cm_l4per_elm_clkctrl = 0x4a009758,
948 .cm_l4per_gpio2_clkctrl = 0x4a009760,
949 .cm_l4per_gpio3_clkctrl = 0x4a009768,
950 .cm_l4per_gpio4_clkctrl = 0x4a009770,
951 .cm_l4per_gpio5_clkctrl = 0x4a009778,
952 .cm_l4per_gpio6_clkctrl = 0x4a009780,
953 .cm_l4per_hdq1w_clkctrl = 0x4a009788,
954 .cm_l4per_i2c1_clkctrl = 0x4a0097a0,
955 .cm_l4per_i2c2_clkctrl = 0x4a0097a8,
956 .cm_l4per_i2c3_clkctrl = 0x4a0097b0,
957 .cm_l4per_i2c4_clkctrl = 0x4a0097b8,
958 .cm_l4per_l4per_clkctrl = 0x4a0097c0,
959 .cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
960 .cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
961 .cm_l4per_mcspi3_clkctrl = 0x4a009800,
962 .cm_l4per_mcspi4_clkctrl = 0x4a009808,
963 .cm_l4per_gpio7_clkctrl = 0x4a009810,
964 .cm_l4per_gpio8_clkctrl = 0x4a009818,
965 .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
966 .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
Matt Porterc97a9b32013-10-07 15:52:59 +0530[diff] [blame]967 .cm_l4per_qspi_clkctrl = 0x4a009838,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]968 .cm_l4per_uart1_clkctrl = 0x4a009840,
969 .cm_l4per_uart2_clkctrl = 0x4a009848,
970 .cm_l4per_uart3_clkctrl = 0x4a009850,
971 .cm_l4per_uart4_clkctrl = 0x4a009858,
972 .cm_l4per_uart5_clkctrl = 0x4a009870,
973 .cm_l4sec_clkstctrl = 0x4a009880,
974 .cm_l4sec_staticdep = 0x4a009884,
975 .cm_l4sec_dynamicdep = 0x4a009888,
976 .cm_l4sec_aes1_clkctrl = 0x4a0098a0,
977 .cm_l4sec_aes2_clkctrl = 0x4a0098a8,
978 .cm_l4sec_des3des_clkctrl = 0x4a0098b0,
979 .cm_l4sec_rng_clkctrl = 0x4a0098c0,
980 .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
981 .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
982
983 /* l4 wkup regs */
984 .cm_abe_pll_ref_clksel = 0x4ae0610c,
985 .cm_sys_clksel = 0x4ae06110,
Lokesh Vutla97405d82013-05-30 03:19:38 +0000[diff] [blame]986 .cm_abe_pll_sys_clksel = 0x4ae06118,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]987 .cm_wkup_clkstctrl = 0x4ae07800,
988 .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
989 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
990 .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
991 .cm_wkup_gpio1_clkctrl = 0x4ae07838,
992 .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
993 .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
994 .cm_wkup_sarram_clkctrl = 0x4ae07860,
995 .cm_wkup_keyboard_clkctrl = 0x4ae07878,
996 .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
997 .prm_rstctrl = 0x4ae07d00,
998 .prm_rstst = 0x4ae07d04,
Lokesh Vutla0b1b60c2013-04-17 20:49:40 +0000[diff] [blame]999 .prm_rsttime = 0x4ae07d08,
Lokesh Vutlaeda6fbc2015-06-04 16:42:36 +0530[diff] [blame]1000 .prm_io_pmctrl = 0x4ae07d20,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]1001 .prm_vc_val_bypass = 0x4ae07da0,
1002 .prm_vc_cfg_i2c_mode = 0x4ae07db4,
1003 .prm_vc_cfg_i2c_clk = 0x4ae07db8,
Nishanth Menon194dd742014-01-14 12:27:29 -0600[diff] [blame]1004
1005 .prm_abbldo_mpu_setup = 0x4AE07DDC,
1006 .prm_abbldo_mpu_ctrl = 0x4AE07DE0,
Nishanth Menone52e3342016-04-21 14:34:25 -0500[diff] [blame]1007 .prm_abbldo_iva_setup = 0x4AE07E34,
1008 .prm_abbldo_iva_ctrl = 0x4AE07E24,
1009 .prm_abbldo_eve_setup = 0x4AE07E30,
1010 .prm_abbldo_eve_ctrl = 0x4AE07E20,
1011 .prm_abbldo_gpu_setup = 0x4AE07DE4,
1012 .prm_abbldo_gpu_ctrl = 0x4AE07DE8,
Vignesh R8a09cfe2015-08-17 13:29:52 +0530[diff] [blame]1013
1014 /*l3main1 edma*/
1015 .cm_l3main1_tptc1_clkctrl = 0x4a008778,
1016 .cm_l3main1_tptc2_clkctrl = 0x4a008780,
Lokesh Vutlad4e41292013-02-17 23:33:37 +0000[diff] [blame]1017};
Nishanth Menon76cff2b2015-08-13 09:51:00 -0500[diff] [blame]1018
1019void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
1020{
1021 u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
1022 (*ctrl)->ctrl_core_sma_sw_0;
1023 clrsetbits_le32(reg, clear_bits, set_bits);
1024}