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Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -04004 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
5 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
6 *
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04007 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040025
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040026/* Board */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040027#define SFFSDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_NAND_LARGEPAGE
29#define CONFIG_SYS_USE_NAND
David Brownell7a4f5112009-05-15 23:47:12 +020030#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
31#define CONFIG_DISPLAY_CPUINFO
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040032/* SoC Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040033#define CONFIG_ARM926EJS /* arm926ejs CPU core */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
35#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
36#define CONFIG_SYS_HZ 1000
David Brownellf7904362009-05-15 23:44:08 +020037#define CONFIG_SOC_DM644X
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040038/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
40#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
41#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
42#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040043/* Memory Info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
45#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
46#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
47#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040048#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
49#define CONFIG_STACKSIZE (256*1024) /* regular stack */
50#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
51#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
52#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040053/* Serial Driver info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_NS16550
55#define CONFIG_SYS_NS16550_SERIAL
David Brownell7ee38c02009-04-12 15:38:06 -070056#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
David Brownell7239c5da2009-04-12 15:40:16 -070058#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040059#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
60#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040062/* I2C Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040063#define CONFIG_HARD_I2C
64#define CONFIG_DRIVER_DAVINCI_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
66#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040067/* Network & Ethernet Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040068#define CONFIG_DRIVER_TI_EMAC
Prakash PMe6441c42010-06-22 10:24:43 -040069#define CONFIG_EMAC_MDIO_PHY_NUM 1
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040070#define CONFIG_MII
71#define CONFIG_BOOTP_DEFAULT
72#define CONFIG_BOOTP_DNS
73#define CONFIG_BOOTP_DNS2
74#define CONFIG_BOOTP_SEND_HOSTNAME
75#define CONFIG_NET_RETRY_COUNT 10
76#define CONFIG_OVERWRITE_ETHADDR_ONCE
Ben Warren84535872009-05-26 00:34:07 -070077#define CONFIG_NET_MULTI
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040078/* Flash & Environment */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020079#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_NO_FLASH
Jean-Christophe PLAGNIOL-VILLARDee4f3e22009-03-30 18:58:39 +020081#define CONFIG_NAND_DAVINCI
Nick Thompson97f4eb82009-12-12 12:12:26 -050082#define CONFIG_SYS_NAND_CS 2
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +020083#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020084#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
Sandeep Paulraja16df2c2009-09-08 17:09:52 -040085#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040086#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
87#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_NAND_BASE 0x02000000
89#define CONFIG_SYS_NAND_HW_ECC
90#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020091#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040092/* I2C switch definitions for PCA9543 chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
94#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
95#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040096/* U-Boot general configuration */
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040097#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040098#define CONFIG_MISC_INIT_R
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040099#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400100#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
103#define CONFIG_SYS_PBSIZE \
104 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
105#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
106#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
107#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400108 * load address. */
109#define CONFIG_VERSION_VARIABLE
110#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
111 * may be later */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_HUSH_PARSER
113#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400114#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LONGHELP
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400116#define CONFIG_CRC32_VERIFY
117#define CONFIG_MX_CYCLIC
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400118/* Linux Information */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400119#define LINUX_BOOT_PARAM_ADDR 0x80000100
120#define CONFIG_CMDLINE_TAG
121#define CONFIG_SETUP_MEMORY_TAGS
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -0400122#define CONFIG_BOOTARGS \
123 "mem=56M " \
124 "console=ttyS0,115200n8 " \
125 "root=/dev/nfs rw noinitrd ip=dhcp " \
126 "nfsroot=${serverip}:/nfsroot/sffsdr " \
127 "eth0=${ethaddr}"
128#define CONFIG_BOOTCOMMAND \
129 "nand read 87A00000 100000 300000;" \
130 "bootelf 87A00000"
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400131/* U-Boot commands */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400132#include <config_cmd_default.h>
133#define CONFIG_CMD_ASKENV
134#define CONFIG_CMD_DHCP
135#define CONFIG_CMD_DIAG
136#define CONFIG_CMD_I2C
137#define CONFIG_CMD_MII
138#define CONFIG_CMD_PING
139#define CONFIG_CMD_SAVES
140#define CONFIG_CMD_NAND
141#define CONFIG_CMD_EEPROM
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400142#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400143#undef CONFIG_CMD_BDI
144#undef CONFIG_CMD_FPGA
145#undef CONFIG_CMD_SETGETDCR
146#undef CONFIG_CMD_FLASH
147#undef CONFIG_CMD_IMLS
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400148/* KGDB support (if any) */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400149#ifdef CONFIG_CMD_KGDB
150#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
151#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
152#endif
153#endif /* __CONFIG_H */