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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach2da0fc02011-01-21 09:31:21 +01006 */
7
8#ifndef __GDSYS_FPGA_H
9#define __GDSYS_FPGA_H
10
Dirk Eibach255ef4d2011-10-20 11:12:55 +020011int init_func_fpga(void);
12
Dirk Eibach2da0fc02011-01-21 09:31:21 +010013enum {
14 FPGA_STATE_DONE_FAILED = 1 << 0,
15 FPGA_STATE_REFLECTION_FAILED = 1 << 1,
Dirk Eibach255ef4d2011-10-20 11:12:55 +020016 FPGA_STATE_PLATFORM = 1 << 2,
Dirk Eibach2da0fc02011-01-21 09:31:21 +010017};
18
19int get_fpga_state(unsigned dev);
20void print_fpga_state(unsigned dev);
21
Dirk Eibachaba27ac2013-06-26 16:04:26 +020022int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
23int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
24
25extern struct ihs_fpga *fpga_ptr[];
26
27#define FPGA_SET_REG(ix, fld, val) \
28 fpga_set_reg((ix), \
29 &fpga_ptr[ix]->fld, \
30 offsetof(struct ihs_fpga, fld), \
31 val)
32
33#define FPGA_GET_REG(ix, fld, val) \
34 fpga_get_reg((ix), \
35 &fpga_ptr[ix]->fld, \
36 offsetof(struct ihs_fpga, fld), \
37 val)
38
Dirk Eibach0e60aa82012-04-27 10:33:46 +020039struct ihs_gpio {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010040 u16 read;
41 u16 clear;
42 u16 set;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020043};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010044
Dirk Eibach0e60aa82012-04-27 10:33:46 +020045struct ihs_i2c {
Dirk Eibachb46226b2014-07-03 09:28:18 +020046 u16 interrupt_status;
47 u16 interrupt_enable;
Dirk Eibach2da0fc02011-01-21 09:31:21 +010048 u16 write_mailbox_ext;
Dirk Eibachb46226b2014-07-03 09:28:18 +020049 u16 write_mailbox;
Dirk Eibach2da0fc02011-01-21 09:31:21 +010050 u16 read_mailbox_ext;
Dirk Eibachb46226b2014-07-03 09:28:18 +020051 u16 read_mailbox;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020052};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010053
Dirk Eibach0e60aa82012-04-27 10:33:46 +020054struct ihs_osd {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010055 u16 version;
56 u16 features;
57 u16 control;
58 u16 xy_size;
Dirk Eibach52158e32011-04-06 13:53:47 +020059 u16 xy_scale;
60 u16 x_pos;
61 u16 y_pos;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020062};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010063
Dirk Eibach50dcf892014-11-13 19:21:18 +010064struct ihs_mdio {
65 u16 control;
66 u16 address_data;
67 u16 rx_data;
68};
69
70struct ihs_io_ep {
71 u16 transmit_data;
72 u16 rx_tx_control;
73 u16 receive_data;
74 u16 rx_tx_status;
75 u16 reserved;
76 u16 device_address;
77 u16 target_address;
78};
79
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000080#ifdef CONFIG_NEO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020081struct ihs_fpga {
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000082 u16 reflection_low; /* 0x0000 */
83 u16 versions; /* 0x0002 */
84 u16 fpga_features; /* 0x0004 */
85 u16 fpga_version; /* 0x0006 */
86 u16 reserved_0[8187]; /* 0x0008 */
87 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +020088};
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000089#endif
90
Dirk Eibach2da0fc02011-01-21 09:31:21 +010091#ifdef CONFIG_IO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020092struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010093 u16 reflection_low; /* 0x0000 */
94 u16 versions; /* 0x0002 */
95 u16 fpga_features; /* 0x0004 */
96 u16 fpga_version; /* 0x0006 */
97 u16 reserved_0[5]; /* 0x0008 */
98 u16 quad_serdes_reset; /* 0x0012 */
99 u16 reserved_1[8181]; /* 0x0014 */
100 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200101};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100102#endif
103
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200104#ifdef CONFIG_IO64
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200105struct ihs_fpga_channel {
106 u16 status_int;
107 u16 config_int;
108 u16 switch_connect_config;
109 u16 tx_destination;
110};
111
112struct ihs_fpga_hicb {
113 u16 status_int;
114 u16 config_int;
115};
116
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200117struct ihs_fpga {
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200118 u16 reflection_low; /* 0x0000 */
119 u16 versions; /* 0x0002 */
120 u16 fpga_features; /* 0x0004 */
121 u16 fpga_version; /* 0x0006 */
122 u16 reserved_0[5]; /* 0x0008 */
123 u16 quad_serdes_reset; /* 0x0012 */
124 u16 reserved_1[502]; /* 0x0014 */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200125 struct ihs_fpga_channel ch[32]; /* 0x0400 */
126 struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
127 u16 reserved_2[7487]; /* 0x0580 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200128 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200129};
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200130#endif
131
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100132#ifdef CONFIG_IOCON
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200133struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100134 u16 reflection_low; /* 0x0000 */
135 u16 versions; /* 0x0002 */
136 u16 fpga_version; /* 0x0004 */
137 u16 fpga_features; /* 0x0006 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100138 u16 reserved_0[1]; /* 0x0008 */
139 u16 top_interrupt; /* 0x000a */
140 u16 reserved_1[4]; /* 0x000c */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200141 struct ihs_gpio gpio; /* 0x0014 */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100142 u16 mpc3w_control; /* 0x001a */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100143 u16 reserved_2[2]; /* 0x001c */
144 struct ihs_io_ep ep; /* 0x0020 */
145 u16 reserved_3[9]; /* 0x002e */
Dirk Eibach071be892015-10-28 11:46:22 +0100146 struct ihs_i2c i2c0; /* 0x0040 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100147 u16 reserved_4[10]; /* 0x004c */
Dirk Eibache50e8962013-07-25 19:28:13 +0200148 u16 mc_int; /* 0x0060 */
149 u16 mc_int_en; /* 0x0062 */
150 u16 mc_status; /* 0x0064 */
151 u16 mc_control; /* 0x0066 */
152 u16 mc_tx_data; /* 0x0068 */
153 u16 mc_tx_address; /* 0x006a */
154 u16 mc_tx_cmd; /* 0x006c */
155 u16 mc_res; /* 0x006e */
156 u16 mc_rx_cmd_status; /* 0x0070 */
157 u16 mc_rx_data; /* 0x0072 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100158 u16 reserved_5[69]; /* 0x0074 */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100159 u16 reflection_high; /* 0x00fe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200160 struct ihs_osd osd; /* 0x0100 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100161 u16 reserved_6[889]; /* 0x010e */
162 u16 videomem[31736]; /* 0x0800 */
163};
164#endif
165
166#ifdef CONFIG_HRCON
167struct ihs_fpga {
168 u16 reflection_low; /* 0x0000 */
169 u16 versions; /* 0x0002 */
170 u16 fpga_version; /* 0x0004 */
171 u16 fpga_features; /* 0x0006 */
172 u16 reserved_0[1]; /* 0x0008 */
173 u16 top_interrupt; /* 0x000a */
174 u16 reserved_1[4]; /* 0x000c */
175 struct ihs_gpio gpio; /* 0x0014 */
176 u16 mpc3w_control; /* 0x001a */
177 u16 reserved_2[2]; /* 0x001c */
178 struct ihs_io_ep ep; /* 0x0020 */
179 u16 reserved_3[9]; /* 0x002e */
Dirk Eibach071be892015-10-28 11:46:22 +0100180 struct ihs_i2c i2c0; /* 0x0040 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100181 u16 reserved_4[10]; /* 0x004c */
182 u16 mc_int; /* 0x0060 */
183 u16 mc_int_en; /* 0x0062 */
184 u16 mc_status; /* 0x0064 */
185 u16 mc_control; /* 0x0066 */
186 u16 mc_tx_data; /* 0x0068 */
187 u16 mc_tx_address; /* 0x006a */
188 u16 mc_tx_cmd; /* 0x006c */
189 u16 mc_res; /* 0x006e */
190 u16 mc_rx_cmd_status; /* 0x0070 */
191 u16 mc_rx_data; /* 0x0072 */
192 u16 reserved_5[69]; /* 0x0074 */
193 u16 reflection_high; /* 0x00fe */
194 struct ihs_osd osd; /* 0x0100 */
195 u16 reserved_6[889]; /* 0x010e */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200196 u16 videomem[31736]; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200197};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100198#endif
199
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +0100200#ifdef CONFIG_STRIDER_CPU
201struct ihs_fpga {
202 u16 reflection_low; /* 0x0000 */
203 u16 versions; /* 0x0002 */
204 u16 fpga_version; /* 0x0004 */
205 u16 fpga_features; /* 0x0006 */
206 u16 reserved_0[1]; /* 0x0008 */
207 u16 top_interrupt; /* 0x000a */
208 u16 reserved_1[3]; /* 0x000c */
209 u16 extended_control; /* 0x0012 */
210 struct ihs_gpio gpio; /* 0x0014 */
211 u16 mpc3w_control; /* 0x001a */
212 u16 reserved_2[2]; /* 0x001c */
213 struct ihs_io_ep ep; /* 0x0020 */
214 u16 reserved_3[9]; /* 0x002e */
215 u16 mc_int; /* 0x0040 */
216 u16 mc_int_en; /* 0x0042 */
217 u16 mc_status; /* 0x0044 */
218 u16 mc_control; /* 0x0046 */
219 u16 mc_tx_data; /* 0x0048 */
220 u16 mc_tx_address; /* 0x004a */
221 u16 mc_tx_cmd; /* 0x004c */
222 u16 mc_res; /* 0x004e */
223 u16 mc_rx_cmd_status; /* 0x0050 */
224 u16 mc_rx_data; /* 0x0052 */
225 u16 reserved_4[62]; /* 0x0054 */
226 struct ihs_i2c i2c0; /* 0x00d0 */
227};
228#endif
229
230#ifdef CONFIG_STRIDER_CON
231struct ihs_fpga {
232 u16 reflection_low; /* 0x0000 */
233 u16 versions; /* 0x0002 */
234 u16 fpga_version; /* 0x0004 */
235 u16 fpga_features; /* 0x0006 */
236 u16 reserved_0[1]; /* 0x0008 */
237 u16 top_interrupt; /* 0x000a */
238 u16 reserved_1[4]; /* 0x000c */
239 struct ihs_gpio gpio; /* 0x0014 */
240 u16 mpc3w_control; /* 0x001a */
241 u16 reserved_2[2]; /* 0x001c */
242 struct ihs_io_ep ep; /* 0x0020 */
243 u16 reserved_3[9]; /* 0x002e */
244 struct ihs_i2c i2c0; /* 0x0040 */
245 u16 reserved_4[10]; /* 0x004c */
246 u16 mc_int; /* 0x0060 */
247 u16 mc_int_en; /* 0x0062 */
248 u16 mc_status; /* 0x0064 */
249 u16 mc_control; /* 0x0066 */
250 u16 mc_tx_data; /* 0x0068 */
251 u16 mc_tx_address; /* 0x006a */
252 u16 mc_tx_cmd; /* 0x006c */
253 u16 mc_res; /* 0x006e */
254 u16 mc_rx_cmd_status; /* 0x0070 */
255 u16 mc_rx_data; /* 0x0072 */
256 u16 reserved_5[70]; /* 0x0074 */
257 struct ihs_osd osd; /* 0x0100 */
258 u16 reserved_6[889]; /* 0x010e */
259 u16 videomem[31736]; /* 0x0800 */
260};
261#endif
262
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100263#ifdef CONFIG_DLVISION_10G
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200264struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100265 u16 reflection_low; /* 0x0000 */
266 u16 versions; /* 0x0002 */
267 u16 fpga_version; /* 0x0004 */
268 u16 fpga_features; /* 0x0006 */
269 u16 reserved_0[10]; /* 0x0008 */
270 u16 extended_interrupt; /* 0x001c */
Dirk Eibachb46226b2014-07-03 09:28:18 +0200271 u16 reserved_1[29]; /* 0x001e */
Dirk Eibach7749c842011-04-06 13:53:48 +0200272 u16 mpc3w_control; /* 0x0058 */
Dirk Eibachb46226b2014-07-03 09:28:18 +0200273 u16 reserved_2[3]; /* 0x005a */
Dirk Eibach071be892015-10-28 11:46:22 +0100274 struct ihs_i2c i2c0; /* 0x0060 */
275 u16 reserved_3[2]; /* 0x006c */
276 struct ihs_i2c i2c1; /* 0x0070 */
277 u16 reserved_4[194]; /* 0x007c */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200278 struct ihs_osd osd; /* 0x0200 */
Dirk Eibach071be892015-10-28 11:46:22 +0100279 u16 reserved_5[761]; /* 0x020e */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200280 u16 videomem[31736]; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200281};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100282#endif
283
284#endif