| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_ROCKCHIP_RK3288=y |
| Masahiro Yamada | 1878095 | 2016-12-07 22:10:25 +0900 | [diff] [blame] | 5 | CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 6 | CONFIG_TARGET_MINIARM_RK3288=y |
| 7 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm" |
| Simon Glass | 98af879 | 2016-10-17 20:12:35 -0600 | [diff] [blame] | 9 | CONFIG_SILENT_CONSOLE=y |
| Simon Glass | ef26d60 | 2016-10-17 20:12:37 -0600 | [diff] [blame] | 10 | CONFIG_CONSOLE_MUX=y |
| 11 | # CONFIG_DISPLAY_CPUINFO is not set |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 12 | CONFIG_SPL_STACK_R=y |
| 13 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 14 | # CONFIG_CMD_IMLS is not set |
| 15 | CONFIG_CMD_MMC=y |
| 16 | CONFIG_CMD_SF=y |
| 17 | CONFIG_CMD_SPI=y |
| 18 | CONFIG_CMD_I2C=y |
| 19 | CONFIG_CMD_GPIO=y |
| 20 | # CONFIG_CMD_SETEXPR is not set |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 21 | CONFIG_CMD_CACHE=y |
| 22 | CONFIG_CMD_TIME=y |
| 23 | CONFIG_CMD_PMIC=y |
| 24 | CONFIG_CMD_REGULATOR=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 25 | CONFIG_SPL_OF_CONTROL=y |
| 26 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 27 | CONFIG_REGMAP=y |
| 28 | CONFIG_SPL_REGMAP=y |
| 29 | CONFIG_SYSCON=y |
| 30 | CONFIG_SPL_SYSCON=y |
| 31 | # CONFIG_SPL_SIMPLE_BUS is not set |
| 32 | CONFIG_CLK=y |
| 33 | CONFIG_SPL_CLK=y |
| 34 | CONFIG_ROCKCHIP_GPIO=y |
| 35 | CONFIG_SYS_I2C_ROCKCHIP=y |
| Masahiro Yamada | 55ed3b4 | 2017-01-10 13:32:04 +0900 | [diff] [blame] | 36 | CONFIG_MMC_DW=y |
| Masahiro Yamada | fed4408 | 2017-01-10 13:32:03 +0900 | [diff] [blame] | 37 | CONFIG_MMC_DW_ROCKCHIP=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 38 | CONFIG_PINCTRL=y |
| 39 | CONFIG_SPL_PINCTRL=y |
| 40 | # CONFIG_SPL_PINCTRL_FULL is not set |
| 41 | CONFIG_ROCKCHIP_RK3288_PINCTRL=y |
| 42 | CONFIG_DM_PMIC=y |
| 43 | CONFIG_PMIC_RK808=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 44 | CONFIG_DM_REGULATOR_FIXED=y |
| Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 45 | CONFIG_REGULATOR_RK808=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 46 | CONFIG_PWM_ROCKCHIP=y |
| 47 | CONFIG_RAM=y |
| 48 | CONFIG_SPL_RAM=y |
| 49 | CONFIG_DEBUG_UART=y |
| 50 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 51 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 52 | CONFIG_DEBUG_UART_SHIFT=2 |
| 53 | CONFIG_SYS_NS16550=y |
| Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 54 | CONFIG_SYSRESET=y |
| Xu Ziyuan | 1c62d99 | 2016-08-01 08:46:19 +0800 | [diff] [blame] | 55 | CONFIG_USE_TINY_PRINTF=y |
| 56 | CONFIG_CMD_DHRYSTONE=y |
| 57 | CONFIG_ERRNO_STR=y |