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stroesec93f7092003-05-23 11:27:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_ASH405 1 /* ...on a ASH405 board */
stroesec93f7092003-05-23 11:27:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroesec93f7092003-05-23 11:27:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
stroesec93f7092003-05-23 11:27:18 +000044
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000049#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
stroesec93f7092003-05-23 11:27:18 +000052
53#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
54#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
55
Matthias Fuchsbd84ee42007-07-09 10:10:06 +020056#define CONFIG_NET_MULTI 1
57#undef CONFIG_HAS_ETH1
58
stroesec93f7092003-05-23 11:27:18 +000059#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000060#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000061#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +020062#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000063
64#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroesec93f7092003-05-23 11:27:18 +000065
stroesec93f7092003-05-23 11:27:18 +000066
Jon Loeliger498ff9a2007-07-05 19:13:52 -050067/*
Jon Loeliger11799432007-07-10 09:02:57 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_IRQ
83#define CONFIG_CMD_ELF
84#define CONFIG_CMD_NAND
85#define CONFIG_CMD_DATE
86#define CONFIG_CMD_I2C
87#define CONFIG_CMD_MII
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_EEPROM
90
stroesec93f7092003-05-23 11:27:18 +000091
wdenkc837dcb2004-01-20 23:12:12 +000092#undef CONFIG_WATCHDOG /* watchdog disabled */
stroesec93f7092003-05-23 11:27:18 +000093
wdenkc837dcb2004-01-20 23:12:12 +000094#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
95#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroesec93f7092003-05-23 11:27:18 +000096
wdenkc837dcb2004-01-20 23:12:12 +000097#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroesec93f7092003-05-23 11:27:18 +000098
99/*
100 * Miscellaneous configurable options
101 */
102#define CFG_LONGHELP /* undef to save memory */
103#define CFG_PROMPT "=> " /* Monitor Command Prompt */
104
105#undef CFG_HUSH_PARSER /* use "hush" command parser */
106#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000107#define CFG_PROMPT_HUSH_PS2 "> "
stroesec93f7092003-05-23 11:27:18 +0000108#endif
109
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500110#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000111#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroesec93f7092003-05-23 11:27:18 +0000112#else
wdenkc837dcb2004-01-20 23:12:12 +0000113#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroesec93f7092003-05-23 11:27:18 +0000114#endif
115#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
116#define CFG_MAXARGS 16 /* max number of command args */
117#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
118
wdenkc837dcb2004-01-20 23:12:12 +0000119#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroesec93f7092003-05-23 11:27:18 +0000120
wdenkc837dcb2004-01-20 23:12:12 +0000121#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesec93f7092003-05-23 11:27:18 +0000122
123#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
124#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
125
wdenkc837dcb2004-01-20 23:12:12 +0000126#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
127#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
128#define CFG_BASE_BAUD 691200
129#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroesec93f7092003-05-23 11:27:18 +0000130
131/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000132#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000133 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
134 57600, 115200, 230400, 460800, 921600 }
stroesec93f7092003-05-23 11:27:18 +0000135
136#define CFG_LOAD_ADDR 0x100000 /* default load address */
137#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
138
wdenkc837dcb2004-01-20 23:12:12 +0000139#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesec93f7092003-05-23 11:27:18 +0000140
141#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
142
wdenkc837dcb2004-01-20 23:12:12 +0000143#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese53cf9432003-06-05 15:39:44 +0000144
wdenkc837dcb2004-01-20 23:12:12 +0000145#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000146
stroesec93f7092003-05-23 11:27:18 +0000147/*-----------------------------------------------------------------------
148 * NAND-FLASH stuff
149 *-----------------------------------------------------------------------
150 */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200151#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
152#define NAND_MAX_CHIPS 1
153#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
154#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100155
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200156#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
157#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
158#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
159#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100160
Matthias Fuchsc750d2e2007-09-12 12:36:53 +0200161#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
162#define CFG_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000163
stroesec93f7092003-05-23 11:27:18 +0000164/*-----------------------------------------------------------------------
165 * PCI stuff
166 *-----------------------------------------------------------------------
167 */
wdenkc837dcb2004-01-20 23:12:12 +0000168#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
169#define PCI_HOST_FORCE 1 /* configure as pci host */
170#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroesec93f7092003-05-23 11:27:18 +0000171
wdenkc837dcb2004-01-20 23:12:12 +0000172#define CONFIG_PCI /* include pci support */
173#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
174#undef CONFIG_PCI_PNP /* do pci plug-and-play */
175 /* resource configuration */
stroesec93f7092003-05-23 11:27:18 +0000176
wdenkc837dcb2004-01-20 23:12:12 +0000177#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroesec93f7092003-05-23 11:27:18 +0000178
wdenkc837dcb2004-01-20 23:12:12 +0000179#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
180#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
181#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
182#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
183#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
184#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
185#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
186#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
187#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesec93f7092003-05-23 11:27:18 +0000188
189/*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
192 * Please note that CFG_SDRAM_BASE _must_ start at 0
193 */
194#define CFG_SDRAM_BASE 0x00000000
195#define CFG_FLASH_BASE 0xFFFC0000
196#define CFG_MONITOR_BASE CFG_FLASH_BASE
197#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
198#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
199
200/*
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
204 */
205#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
209#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
210#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
211
212#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
213#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
214
wdenkc837dcb2004-01-20 23:12:12 +0000215#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
216#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
217#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesec93f7092003-05-23 11:27:18 +0000218/*
219 * The following defines are added for buggy IOP480 byte interface.
220 * All other boards should use the standard values (CPCI405 etc.)
221 */
wdenkc837dcb2004-01-20 23:12:12 +0000222#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
223#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
224#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroesec93f7092003-05-23 11:27:18 +0000225
wdenkc837dcb2004-01-20 23:12:12 +0000226#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesec93f7092003-05-23 11:27:18 +0000227
228#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000229#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
230#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroesec93f7092003-05-23 11:27:18 +0000231#endif
232
233/*-----------------------------------------------------------------------
234 * Environment Variable setup
235 */
wdenkc837dcb2004-01-20 23:12:12 +0000236#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
237#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
238#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000239 /* total size of a CAT24WC16 is 2048 bytes */
stroesec93f7092003-05-23 11:27:18 +0000240
241#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000242#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroesec93f7092003-05-23 11:27:18 +0000243
244/*-----------------------------------------------------------------------
245 * I2C EEPROM (CAT24WC16) for environment
246 */
247#define CONFIG_HARD_I2C /* I2c with hardware support */
248#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
249#define CFG_I2C_SLAVE 0x7F
250
251#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000252#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
253/* mask of address bits that overflow into the "EEPROM chip address" */
stroesec93f7092003-05-23 11:27:18 +0000254#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
255#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
256 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000257 /* last 4 bits of the address */
stroesec93f7092003-05-23 11:27:18 +0000258#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
259#define CFG_EEPROM_PAGE_WRITE_ENABLE
260
261/*-----------------------------------------------------------------------
262 * Cache Configuration
263 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200264#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkc837dcb2004-01-20 23:12:12 +0000265 /* have only 8kB, 16kB is save here */
stroesec93f7092003-05-23 11:27:18 +0000266#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500267#if defined(CONFIG_CMD_KGDB)
stroesec93f7092003-05-23 11:27:18 +0000268#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
269#endif
270
271/*
272 * Init Memory Controller:
273 *
274 * BR0/1 and OR0/1 (FLASH)
275 */
276
277#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
278
279/*-----------------------------------------------------------------------
280 * External Bus Controller (EBC) Setup
281 */
282
wdenkc837dcb2004-01-20 23:12:12 +0000283/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
284#define CFG_EBC_PB0AP 0x92015480
285/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
286#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesec93f7092003-05-23 11:27:18 +0000287
wdenkc837dcb2004-01-20 23:12:12 +0000288/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
289#define CFG_EBC_PB1AP 0x92015480
290#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroesec93f7092003-05-23 11:27:18 +0000291
wdenkc837dcb2004-01-20 23:12:12 +0000292/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
293#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
294#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesec93f7092003-05-23 11:27:18 +0000295
wdenkc837dcb2004-01-20 23:12:12 +0000296/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
297#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
298#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesec93f7092003-05-23 11:27:18 +0000299
wdenkc837dcb2004-01-20 23:12:12 +0000300#define CAN_BA 0xF0000000 /* CAN Base Address */
301#define DUART0_BA 0xF0000400 /* DUART Base Address */
302#define DUART1_BA 0xF0000408 /* DUART Base Address */
303#define DUART2_BA 0xF0000410 /* DUART Base Address */
304#define DUART3_BA 0xF0000418 /* DUART Base Address */
305#define RTC_BA 0xF0000500 /* RTC Base Address */
306#define CFG_NAND_BASE 0xF4000000
stroesec93f7092003-05-23 11:27:18 +0000307
308/*-----------------------------------------------------------------------
309 * FPGA stuff
310 */
wdenkc837dcb2004-01-20 23:12:12 +0000311#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
312#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroesec93f7092003-05-23 11:27:18 +0000313
314/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000315#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
316#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
317#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
318#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
319#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesec93f7092003-05-23 11:27:18 +0000320
321/*-----------------------------------------------------------------------
322 * Definitions for initial stack pointer and data area (in data cache)
323 */
324/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000325#define CFG_TEMP_STACK_OCM 1
stroesec93f7092003-05-23 11:27:18 +0000326
327/* On Chip Memory location */
328#define CFG_OCM_DATA_ADDR 0xF8000000
329#define CFG_OCM_DATA_SIZE 0x1000
330#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
331#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
332
333#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
334#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000335#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroesec93f7092003-05-23 11:27:18 +0000336
337/*-----------------------------------------------------------------------
338 * Definitions for GPIO setup (PPC405EP specific)
339 *
wdenkc837dcb2004-01-20 23:12:12 +0000340 * GPIO0[0] - External Bus Controller BLAST output
341 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroesec93f7092003-05-23 11:27:18 +0000342 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
343 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
344 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
345 * GPIO0[24-27] - UART0 control signal inputs/outputs
346 * GPIO0[28-29] - UART1 data signal input/output
347 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
348 */
wdenkc837dcb2004-01-20 23:12:12 +0000349#define CFG_GPIO0_OSRH 0x40000550
350#define CFG_GPIO0_OSRL 0x00000110
351#define CFG_GPIO0_ISR1H 0x00000000
352#define CFG_GPIO0_ISR1L 0x15555445
353#define CFG_GPIO0_TSRH 0x00000000
354#define CFG_GPIO0_TSRL 0x00000000
355#define CFG_GPIO0_TCR 0xF7FE0014
stroesec93f7092003-05-23 11:27:18 +0000356
wdenkc837dcb2004-01-20 23:12:12 +0000357#define CFG_DUART_RST (0x80000000 >> 14)
stroesec93f7092003-05-23 11:27:18 +0000358
359/*
360 * Internal Definitions
361 *
362 * Boot Flags
363 */
364#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
365#define BOOTFLAG_WARM 0x02 /* Software reboot */
366
367/*
368 * Default speed selection (cpu_plb_opb_ebc) in mhz.
369 * This value will be set if iic boot eprom is disabled.
370 */
371#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000372#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
373#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroesec93f7092003-05-23 11:27:18 +0000374#endif
375#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000376#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
377#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroesec93f7092003-05-23 11:27:18 +0000378#endif
379#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000380#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
381#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroesec93f7092003-05-23 11:27:18 +0000382#endif
383
384#endif /* __CONFIG_H */