blob: 376973b94da0b06e4b7570c31a982e25112a1810 [file] [log] [blame]
Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#undef DEBUG
13
14/*
15 * High Level Configuration Options
16 */
17#define CONFIG_E300 1 /* E300 family */
18#define CONFIG_QE 1 /* Has QE */
19#define CONFIG_MPC83XX 1 /* MPC83xx family */
20#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
21
22#define CONFIG_PCI 1
23#define CONFIG_83XX_GENERIC_PCI 1
24
25/*
26 * System Clock Setup
27 */
28#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
29
30#ifndef CONFIG_SYS_CLK_FREQ
31#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
32#endif
33
34/*
35 * Hardware Reset Configuration Word
36 */
37#define CFG_HRCW_LOW (\
38 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39 HRCWL_DDR_TO_SCB_CLK_2X1 |\
40 HRCWL_VCO_1X2 |\
41 HRCWL_CSB_TO_CLKIN_2X1 |\
42 HRCWL_CORE_TO_CSB_2_5X1 |\
43 HRCWL_CE_PLL_VCO_DIV_2 |\
44 HRCWL_CE_PLL_DIV_1X1 |\
45 HRCWL_CE_TO_PLL_1X3)
46
47#define CFG_HRCW_HIGH (\
48 HRCWH_PCI_HOST |\
49 HRCWH_PCI1_ARBITER_ENABLE |\
50 HRCWH_CORE_ENABLE |\
51 HRCWH_FROM_0X00000100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_BIG_ENDIAN |\
56 HRCWH_LALE_NORMAL)
57
58/*
59 * System IO Config
60 */
61#define CFG_SICRL 0x00000000
62
63#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
64
65/*
66 * IMMR new address
67 */
68#define CFG_IMMR 0xE0000000
69
70/*
71 * DDR Setup
72 */
73#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
74#define CFG_SDRAM_BASE CFG_DDR_BASE
75#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
76#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
77
78#undef CONFIG_SPD_EEPROM
79#if defined(CONFIG_SPD_EEPROM)
80/* Determine DDR configuration from I2C interface
81 */
82#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
83#else
84/* Manually set up DDR parameters
85 */
86#define CFG_DDR_SIZE 64 /* MB */
87#define CFG_DDR_CS0_CONFIG 0x80840101
88#define CFG_DDR_TIMING_0 0x00220802
89#define CFG_DDR_TIMING_1 0x3935d322
90#define CFG_DDR_TIMING_2 0x0f9048ca
91#define CFG_DDR_TIMING_3 0x00000000
92#define CFG_DDR_CLK_CNTL 0x02000000
93#define CFG_DDR_MODE 0x44400232
94#define CFG_DDR_MODE2 0x8000c000
95#define CFG_DDR_INTERVAL 0x03200064
96#define CFG_DDR_CS0_BNDS 0x00000003
97#define CFG_DDR_SDRAM_CFG 0x43080000
98#define CFG_DDR_SDRAM_CFG2 0x00401000
99#endif
100
101/*
102 * Memory test
103 */
104#undef CFG_DRAM_TEST /* memory test, takes time */
105#define CFG_MEMTEST_START 0x00030000 /* memtest region */
106#define CFG_MEMTEST_END 0x03f00000
107
108/*
109 * The reserved memory
110 */
111#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
112
113#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
114#define CFG_RAMBOOT
115#else
116#undef CFG_RAMBOOT
117#endif
118
119#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
120#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
121
122/*
123 * Initial RAM Base Address Setup
124 */
125#define CFG_INIT_RAM_LOCK 1
126#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
127#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
128#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
129#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
130
131/*
132 * Local Bus Configuration & Clock Setup
133 */
134#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
135#define CFG_LBC_LBCR 0x00000000
136
137/*
138 * FLASH on the Local Bus
139 */
140#define CFG_FLASH_CFI /* use the Common Flash Interface */
141#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
142#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
143#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
144
145#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
146#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
147
148#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
149 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
150 BR_V) /* valid */
151#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
152
153#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
154#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
155
156#undef CFG_FLASH_CHECKSUM
157
158/*
159 * SDRAM on the Local Bus
160 */
161#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
162
163#ifdef CFG_LB_SDRAM
164#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
165#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
166
167#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
168#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
169
170/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
171/*
172 * Base Register 2 and Option Register 2 configure SDRAM.
173 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
174 *
175 * For BR2, need:
176 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
177 * port size = 32-bits = BR2[19:20] = 11
178 * no parity checking = BR2[21:22] = 00
179 * SDRAM for MSEL = BR2[24:26] = 011
180 * Valid = BR[31] = 1
181 *
182 * 0 4 8 12 16 20 24 28
183 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
184 *
185 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
186 * the top 17 bits of BR2.
187 */
188
189#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
190
191/*
192 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
193 *
194 * For OR2, need:
195 * 64MB mask for AM, OR2[0:7] = 1111 1100
196 * XAM, OR2[17:18] = 11
197 * 9 columns OR2[19-21] = 010
198 * 13 rows OR2[23-25] = 100
199 * EAD set for extra time OR[31] = 1
200 *
201 * 0 4 8 12 16 20 24 28
202 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
203 */
204
205#define CFG_OR2_PRELIM 0xfc006901
206
207#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
208#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
209
210/*
211 * LSDMR masks
212 */
213#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
214#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
215#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
216#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
217#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
218#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
219#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
220#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
221
222#define CFG_LBC_LSDMR_COMMON 0x0063b723
223
224/*
225 * SDRAM Controller configuration sequence.
226 */
227#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
228 | CFG_LBC_LSDMR_OP_PCHALL)
229#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
230 | CFG_LBC_LSDMR_OP_ARFRSH)
231#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
232 | CFG_LBC_LSDMR_OP_ARFRSH)
233#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
234 | CFG_LBC_LSDMR_OP_MRW)
235#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
236 | CFG_LBC_LSDMR_OP_NORMAL)
237
238#endif
239
240/*
241 * Windows to access PIB via local bus
242 */
243#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
244#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
245
246/*
247 * Serial Port
248 */
249#define CONFIG_CONS_INDEX 1
250#undef CONFIG_SERIAL_SOFTWARE_FIFO
251#define CFG_NS16550
252#define CFG_NS16550_SERIAL
253#define CFG_NS16550_REG_SIZE 1
254#define CFG_NS16550_CLK get_bus_freq(0)
255
256#define CFG_BAUDRATE_TABLE \
257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
258
259#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
260#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
261
262#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
263/* Use the HUSH parser */
264#define CFG_HUSH_PARSER
265#ifdef CFG_HUSH_PARSER
266#define CFG_PROMPT_HUSH_PS2 "> "
267#endif
268
269/* pass open firmware flat tree */
270#define CONFIG_OF_LIBFDT 1
271#define CONFIG_OF_BOARD_SETUP 1
272
273#define OF_CPU "PowerPC,8323@0"
274#define OF_SOC "soc8323@e0000000"
275#define OF_QE "qe@e0100000"
276#define OF_TBCLK (bd->bi_busfreq / 4)
277#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
278
279/* I2C */
280#define CONFIG_HARD_I2C /* I2C with hardware support */
281#undef CONFIG_SOFT_I2C /* I2C bit-banged */
282#define CONFIG_FSL_I2C
283#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
284#define CFG_I2C_SLAVE 0x7F
285#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
286#define CFG_I2C_OFFSET 0x3000
287
288/*
289 * Config on-board RTC
290 */
291#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
292#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
293
294/*
295 * General PCI
296 * Addresses are mapped 1-1.
297 */
298#define CFG_PCI1_MEM_BASE 0x80000000
299#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
300#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
301#define CFG_PCI1_MMIO_BASE 0x90000000
302#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
303#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
304#define CFG_PCI1_IO_BASE 0xd0000000
305#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
306#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
307
308#ifdef CONFIG_PCI
309
310#define CONFIG_NET_MULTI
311#define CONFIG_PCI_PNP /* do pci plug-and-play */
312
313#undef CONFIG_EEPRO100
314#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
315#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
316
317#endif /* CONFIG_PCI */
318
319
320#ifndef CONFIG_NET_MULTI
321#define CONFIG_NET_MULTI 1
322#endif
323
324/*
325 * QE UEC ethernet configuration
326 */
327#define CONFIG_UEC_ETH
328#define CONFIG_ETHPRIME "Freescale GETH"
329
330#define CONFIG_UEC_ETH1 /* ETH3 */
331
332#ifdef CONFIG_UEC_ETH1
333#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
334#define CFG_UEC1_RX_CLK QE_CLK9
335#define CFG_UEC1_TX_CLK QE_CLK10
336#define CFG_UEC1_ETH_TYPE FAST_ETH
337#define CFG_UEC1_PHY_ADDR 4
338#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
339#endif
340
341#define CONFIG_UEC_ETH2 /* ETH4 */
342
343#ifdef CONFIG_UEC_ETH2
344#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
345#define CFG_UEC2_RX_CLK QE_CLK16
346#define CFG_UEC2_TX_CLK QE_CLK3
347#define CFG_UEC2_ETH_TYPE FAST_ETH
348#define CFG_UEC2_PHY_ADDR 0
349#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
350#endif
351
352/*
353 * Environment
354 */
355#ifndef CFG_RAMBOOT
356 #define CFG_ENV_IS_IN_FLASH 1
357 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
358 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
359 #define CFG_ENV_SIZE 0x2000
360#else
361 #define CFG_NO_FLASH 1 /* Flash is not usable now */
362 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
363 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
364 #define CFG_ENV_SIZE 0x2000
365#endif
366
367#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
368#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
369
370/*
371 * BOOTP options
372 */
373#define CONFIG_BOOTP_BOOTFILESIZE
374#define CONFIG_BOOTP_BOOTPATH
375#define CONFIG_BOOTP_GATEWAY
376#define CONFIG_BOOTP_HOSTNAME
377
378/*
379 * Command line configuration.
380 */
381#include <config_cmd_default.h>
382
383#define CONFIG_CMD_PING
384#define CONFIG_CMD_I2C
385#define CONFIG_CMD_ASKENV
386
387#if defined(CONFIG_PCI)
388 #define CONFIG_CMD_PCI
389#endif
390#if defined(CFG_RAMBOOT)
391 #undef CONFIG_CMD_ENV
392 #undef CONFIG_CMD_LOADS
393#endif
394
395#undef CONFIG_WATCHDOG /* watchdog disabled */
396
397/*
398 * Miscellaneous configurable options
399 */
400#define CFG_LONGHELP /* undef to save memory */
401#define CFG_LOAD_ADDR 0x2000000 /* default load address */
402#define CFG_PROMPT "=> " /* Monitor Command Prompt */
403
404#if (CONFIG_CMD_KGDB)
405 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
406#else
407 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
408#endif
409
410#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
411#define CFG_MAXARGS 16 /* max number of command args */
412#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
413#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
414
415/*
416 * For booting Linux, the board info and command line data
417 * have to be in the first 8 MB of memory, since this is
418 * the maximum mapped by the Linux kernel during initialization.
419 */
420#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
421
422/*
423 * Core HID Setup
424 */
425#define CFG_HID0_INIT 0x000000000
426#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
427#define CFG_HID2 HID2_HBE
428
429/*
430 * Cache Config
431 */
432#define CFG_DCACHE_SIZE 16384
433#define CFG_CACHELINE_SIZE 32
434#if defined(CONFIG_CMD_KGDB)
435#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
436#endif
437
438/*
439 * MMU Setup
440 */
441
442/* DDR: cache cacheable */
443#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
444#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
445#define CFG_DBAT0L CFG_IBAT0L
446#define CFG_DBAT0U CFG_IBAT0U
447
448/* IMMRBAR & PCI IO: cache-inhibit and guarded */
449#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
450 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
451#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
452#define CFG_DBAT1L CFG_IBAT1L
453#define CFG_DBAT1U CFG_IBAT1U
454
455/* FLASH: icache cacheable, but dcache-inhibit and guarded */
456#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
457#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
458#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \
459 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
460#define CFG_DBAT2U CFG_IBAT2U
461
462#define CFG_IBAT3L (0)
463#define CFG_IBAT3U (0)
464#define CFG_DBAT3L CFG_IBAT3L
465#define CFG_DBAT3U CFG_IBAT3U
466
467/* Stack in dcache: cacheable, no memory coherence */
468#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
469#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
470#define CFG_DBAT4L CFG_IBAT4L
471#define CFG_DBAT4U CFG_IBAT4U
472
473#ifdef CONFIG_PCI
474/* PCI MEM space: cacheable */
475#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
476#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
477#define CFG_DBAT5L CFG_IBAT5L
478#define CFG_DBAT5U CFG_IBAT5U
479/* PCI MMIO space: cache-inhibit and guarded */
480#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
481 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
482#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
483#define CFG_DBAT6L CFG_IBAT6L
484#define CFG_DBAT6U CFG_IBAT6U
485#else
486#define CFG_IBAT5L (0)
487#define CFG_IBAT5U (0)
488#define CFG_IBAT6L (0)
489#define CFG_IBAT6U (0)
490#define CFG_DBAT5L CFG_IBAT5L
491#define CFG_DBAT5U CFG_IBAT5U
492#define CFG_DBAT6L CFG_IBAT6L
493#define CFG_DBAT6U CFG_IBAT6U
494#endif
495
496/* Nothing in BAT7 */
497#define CFG_IBAT7L (0)
498#define CFG_IBAT7U (0)
499#define CFG_DBAT7L CFG_IBAT7L
500#define CFG_DBAT7U CFG_IBAT7U
501
502/*
503 * Internal Definitions
504 *
505 * Boot Flags
506 */
507#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
508#define BOOTFLAG_WARM 0x02 /* Software reboot */
509
510#if (CONFIG_CMD_KGDB)
511#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
512#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
513#endif
514
515/*
516 * Environment Configuration
517 */
518#define CONFIG_ENV_OVERWRITE
519
520#define CONFIG_ETHADDR 00:04:9f:ef:03:01
521#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
522#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
523
524#define CONFIG_IPADDR 10.0.0.2
525#define CONFIG_SERVERIP 10.0.0.1
526#define CONFIG_GATEWAYIP 10.0.0.1
527#define CONFIG_NETMASK 255.0.0.0
528#define CONFIG_NETDEV eth1
529
530#define CONFIG_HOSTNAME mpc8323erdb
531#define CONFIG_ROOTPATH /nfsroot
532#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
533#define CONFIG_BOOTFILE uImage
534#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
535#define CONFIG_FDTFILE mpc832x_rdb.dtb
536
537#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
538#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
539#define CONFIG_BAUDRATE 115200
540
541#define XMK_STR(x) #x
542#define MK_STR(x) XMK_STR(x)
543
544#define CONFIG_EXTRA_ENV_SETTINGS \
545 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
546 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
547 "tftpflash=tftp $loadaddr $uboot;" \
548 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
549 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
550 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
551 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
552 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
553 "fdtaddr=400000\0" \
554 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
555 "ramdiskaddr=1000000\0" \
556 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
557 "console=ttyS0\0" \
558 "setbootargs=setenv bootargs " \
559 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
560 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
561 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
562 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
563
564#define CONFIG_NFSBOOTCOMMAND \
565 "setenv rootdev /dev/nfs;" \
566 "run setbootargs;" \
567 "run setipargs;" \
568 "tftp $loadaddr $bootfile;" \
569 "tftp $fdtaddr $fdtfile;" \
570 "bootm $loadaddr - $fdtaddr"
571
572#define CONFIG_RAMBOOTCOMMAND \
573 "setenv rootdev /dev/ram;" \
574 "run setbootargs;" \
575 "tftp $ramdiskaddr $ramdiskfile;" \
576 "tftp $loadaddr $bootfile;" \
577 "tftp $fdtaddr $fdtfile;" \
578 "bootm $loadaddr $ramdiskaddr $fdtaddr"
579
580#undef MK_STR
581#undef XMK_STR
582
583#endif /* __CONFIG_H */