blob: 8f18c9f1b1bfc4ed36f17deeed4728ccad81ed59 [file] [log] [blame]
wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * Configuation settings for the LART board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
wdenkda27dcf2002-09-10 19:19:06 +000031 * High Level Configuration Options
32 * (easy to change)
33 */
34#define CONFIG_SA1100 1 /* This is an SA1100 CPU */
35#define CONFIG_LART 1 /* on an LART Board */
36
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38
39/*
40 * Size of malloc() pool
41 */
wdenk699b13a2002-11-03 18:03:52 +000042#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000043#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenkda27dcf2002-09-10 19:19:06 +000044
45/*
46 * Hardware drivers
47 */
48#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
49#define CS8900_BASE 0x20008300
50#define CS8900_BUS16 1
51
52/*
53 * select serial console configuration
54 */
55#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on LART */
56
57/* allow to overwrite serial and ethaddr */
58#define CONFIG_ENV_OVERWRITE
59
60#define CONFIG_BAUDRATE 9600
61
wdenkda27dcf2002-09-10 19:19:06 +000062
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050063/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
71
72/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050073 * Command line configuration.
74 */
75#include <config_cmd_default.h>
76
wdenkda27dcf2002-09-10 19:19:06 +000077
78#define CONFIG_BOOTDELAY 3
79#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
80#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
81#define CONFIG_NETMASK 255.255.0.0
82#define CONFIG_IPADDR 172.22.2.131
83#define CONFIG_SERVERIP 172.22.2.126
84#define CONFIG_BOOTFILE "elinos-lart"
85#define CONFIG_BOOTCOMMAND "tftp; bootm"
86
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050087#if defined(CONFIG_CMD_KGDB)
wdenkda27dcf2002-09-10 19:19:06 +000088#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
89#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
90#endif
91
92/*
93 * Miscellaneous configurable options
94 */
95#define CFG_LONGHELP /* undef to save memory */
96#define CFG_PROMPT "LART # " /* Monitor Command Prompt */
97#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
98#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
99#define CFG_MAXARGS 16 /* max number of command args */
100#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
101
102#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
103#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
104
105#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
106
107#define CFG_LOAD_ADDR 0xc8000000 /* default load address */
108
109#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
110#define CFG_CPUSPEED 0x0b /* set core clock to 220 MHz */
111
112 /* valid baudrates */
113#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
114
115/*-----------------------------------------------------------------------
116 * Stack sizes
117 *
118 * The stack sizes are set up in start.S using the settings below
119 */
120#define CONFIG_STACKSIZE (128*1024) /* regular stack */
121#ifdef CONFIG_USE_IRQ
122#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
123#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
124#endif
125
126/*-----------------------------------------------------------------------
127 * Physical Memory Map
128 */
129#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
130#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
131#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
132#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */
133#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
134#define PHYS_SDRAM_3 0xc8000000 /* SDRAM Bank #3 */
135#define PHYS_SDRAM_3_SIZE 0x00800000 /* 8 MB */
136#define PHYS_SDRAM_4 0xc9000000 /* SDRAM Bank #4 */
137#define PHYS_SDRAM_4_SIZE 0x00800000 /* 8 MB */
138
139
140#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
141#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
142
143#define CFG_FLASH_BASE PHYS_FLASH_1
144
145/*-----------------------------------------------------------------------
146 * FLASH and environment organization
147 */
148#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
149#define CFG_MAX_FLASH_SECT (31+8) /* max number of sectors on one chip */
150
151/* timeout values are in ticks */
152#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
153#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
154
155#define CFG_ENV_IS_IN_FLASH 1
156#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
157#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
158
159#endif /* __CONFIG_H */