blob: 2b2d37751e0901d46514f2cc2ad5895d144c846f [file] [log] [blame]
wdenk52f52c12003-06-19 23:04:19 +00001/*
2 * (C) Copyright 2003
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Logotronic DL board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/logodl.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk52f52c12003-06-19 23:04:19 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
39
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
42/*
43 * Hardware drivers
44 */
45
46/*
47 * select serial console configuration
48 */
49#define CONFIG_FFUART 1 /* we use FFUART */
50
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53
54#define CONFIG_BAUDRATE 19200
wdenk993cad92003-06-26 22:04:09 +000055#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
wdenk52f52c12003-06-19 23:04:19 +000056
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050057
58/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050059 * BOOTP options
60 */
61#define CONFIG_BOOTP_BOOTFILESIZE
62#define CONFIG_BOOTP_BOOTPATH
63#define CONFIG_BOOTP_GATEWAY
64#define CONFIG_BOOTP_HOSTNAME
65
66
67/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050068 * Command line configuration.
69 */
70#define CONFIG_CMD_ASKENV
71#define CONFIG_CMD_ECHO
72#define CONFIG_CMD_ENV
73#define CONFIG_CMD_FLASH
74#define CONFIG_CMD_MEMORY
75#define CONFIG_CMD_RUN
76
wdenk52f52c12003-06-19 23:04:19 +000077
78#define CONFIG_BOOTDELAY 3
79/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
80#define CONFIG_BOOTARGS "console=ttyS0,19200"
81#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
82#define CONFIG_NETMASK 255.255.255.0
83#define CONFIG_IPADDR 192.168.1.56
84#define CONFIG_SERVERIP 192.168.1.2
85#define CONFIG_BOOTCOMMAND "bootm 0x40000"
86#define CONFIG_SHOW_BOOT_PROGRESS
87
88#define CONFIG_CMDLINE_TAG 1
89
90/*
91 * Miscellaneous configurable options
92 */
93
94/*
95 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
96 * used for the RAM copy of the uboot code
97 *
98 */
99#define CFG_MALLOC_LEN (256*1024)
100
101#define CFG_LONGHELP /* undef to save memory */
102#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
103#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105#define CFG_MAXARGS 16 /* max number of command args */
106#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107
108#define CFG_MEMTEST_START 0x08000000 /* memtest works on */
109#define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */
110
111#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
112
113#define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */
114
115#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
116 /* RS: the oscillator is actually 3680130?? */
117
118#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
119 /* 0101000001 */
120 /* ^^^^^ Memory Speed 99.53 MHz */
121 /* ^^ Run Mode Speed = 2x Mem Speed */
122 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
123
124#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
125
wdenk8bde7f72003-06-27 21:31:46 +0000126 /* valid baudrates */
wdenk52f52c12003-06-19 23:04:19 +0000127#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
128
129/*
130 * SMSC91C111 Network Card
131 */
wdenk993cad92003-06-26 22:04:09 +0000132#if 0
133#define CONFIG_DRIVER_SMC91111 1
134#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
135#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
136#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
137#undef CONFIG_SHOW_ACTIVITY
138#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
139#endif
wdenk52f52c12003-06-19 23:04:19 +0000140
141/*
142 * Stack sizes
143 *
144 * The stack sizes are set up in start.S using the settings below
145 */
146#define CONFIG_STACKSIZE (128*1024) /* regular stack */
147#ifdef CONFIG_USE_IRQ
148#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
149#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
150#endif
151
152/*
153 * Physical Memory Map
154 */
155#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
156#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
157#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
158
159#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
160#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
161#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
162
163#define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
164#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
165
166#define CFG_FLASH_BASE PHYS_FLASH_1
167
168
169/*
170 * GPIO settings
171 *
172 * GP?? == FOOBAR is 0/1
173 */
174
175#define _BIT0 0x00000001
176#define _BIT1 0x00000002
177#define _BIT2 0x00000004
178#define _BIT3 0x00000008
179
180#define _BIT4 0x00000010
181#define _BIT5 0x00000020
182#define _BIT6 0x00000040
183#define _BIT7 0x00000080
184
185#define _BIT8 0x00000100
186#define _BIT9 0x00000200
187#define _BIT10 0x00000400
188#define _BIT11 0x00000800
189
190#define _BIT12 0x00001000
191#define _BIT13 0x00002000
192#define _BIT14 0x00004000
193#define _BIT15 0x00008000
194
195#define _BIT16 0x00010000
196#define _BIT17 0x00020000
197#define _BIT18 0x00040000
198#define _BIT19 0x00080000
199
200#define _BIT20 0x00100000
201#define _BIT21 0x00200000
202#define _BIT22 0x00400000
203#define _BIT23 0x00800000
204
205#define _BIT24 0x01000000
206#define _BIT25 0x02000000
207#define _BIT26 0x04000000
208#define _BIT27 0x08000000
209
210#define _BIT28 0x10000000
211#define _BIT29 0x20000000
212#define _BIT30 0x40000000
213#define _BIT31 0x80000000
214
215
216#define CFG_LED_A_BIT (_BIT18)
217#define CFG_LED_A_SR GPSR0
218#define CFG_LED_A_CR GPCR0
219
220#define CFG_LED_B_BIT (_BIT16)
221#define CFG_LED_B_SR GPSR1
222#define CFG_LED_B_CR GPCR1
223
224
225/* LED A: off, LED B: off */
226#define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
227#define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
228#define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
229
230#define CFG_GPCR0_VAL 0x00000000
231#define CFG_GPCR1_VAL 0x00000000
232#define CFG_GPCR2_VAL 0x00000000
233
234#define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
235#define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
236#define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
237
238#define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
239#define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
wdenk8bde7f72003-06-27 21:31:46 +0000240 _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
wdenk52f52c12003-06-19 23:04:19 +0000241#define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
wdenk8bde7f72003-06-27 21:31:46 +0000242 _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
wdenk52f52c12003-06-19 23:04:19 +0000243#define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
244#define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
wdenk8bde7f72003-06-27 21:31:46 +0000245 _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
wdenk52f52c12003-06-19 23:04:19 +0000246#define CFG_GAFR2_U_VAL (_BIT1)
247
248#define CFG_PSSR_VAL (0x20)
249
250/*
251 * Memory settings
252 */
253#define CFG_MSC0_VAL 0x123c2980
254#define CFG_MSC1_VAL 0x123c2661
255#define CFG_MSC2_VAL 0x7ff87ff8
256
257
258/* no sdram/pcmcia here */
259#define CFG_MDCNFG_VAL 0x00000000
260#define CFG_MDREFR_VAL 0x00000000
261#define CFG_MDREFR_VAL_100 0x00000000
262#define CFG_MDMRS_VAL 0x00000000
263
264/* only SRAM */
265#define SXCNFG_SETTINGS 0x00000000
266
267/*
268 * PCMCIA and CF Interfaces
269 */
270
271#define CFG_MECR_VAL 0x00000000
272#define CFG_MCMEM0_VAL 0x00010504
273#define CFG_MCMEM1_VAL 0x00010504
274#define CFG_MCATT0_VAL 0x00010504
275#define CFG_MCATT1_VAL 0x00010504
276#define CFG_MCIO0_VAL 0x00004715
277#define CFG_MCIO1_VAL 0x00004715
278
279
280/*
281 * FLASH and environment organization
282 */
283#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
284#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
285
286/* timeout values are in ticks */
287#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
288#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
289
290/* FIXME */
291#define CFG_ENV_IS_IN_FLASH 1
292#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
293#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
294
295#endif /* __CONFIG_H */