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wdenk6c7a1402004-07-11 19:17:20 +00001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <pci.h>
30
31#include "sdram.h"
32
33#if CONFIG_TOTAL5200_REV==2
34#include "mt48lc32m16a2-75.h"
35#else
36#include "mt48lc16m16a2-75.h"
37#endif
38
39long int initdram (int board_type)
40{
41 sdram_conf_t sdram_conf;
42
43 sdram_conf.ddr = SDRAM_DDR;
44 sdram_conf.mode = SDRAM_MODE;
45 sdram_conf.emode = 0;
46 sdram_conf.control = SDRAM_CONTROL;
47 sdram_conf.config1 = SDRAM_CONFIG1;
48 sdram_conf.config2 = SDRAM_CONFIG2;
49#if defined(CONFIG_MPC5200)
50 sdram_conf.tapdelay = 0;
51#endif
52#if defined(CONFIG_MGT5100)
53 sdram_conf.addrsel = SDRAM_ADDRSEL;
54#endif
55 return mpc5xxx_sdram_init (&sdram_conf);
56}
57
58int checkboard (void)
59{
60#if defined(CONFIG_MPC5200)
61#if CONFIG_TOTAL5200_REV==2
62 puts ("Board: Total5200 Rev.2 ");
63#else
64 puts ("Board: Total5200 ");
65#endif
66#elif defined(CONFIG_MGT5100)
67 puts ("Board: Total5100 ");
68#endif
69
70/*
71 * Retrieve FPGA Revision.
72 */
73printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400));
74
75/*
76 * Take all peripherals in power-up mode.
77 */
78#if CONFIG_TOTAL5200_REV==2
79 *(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70;
80#else
81 *(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70;
82#endif
83
84 return 0;
85}
86
87#if defined(CONFIG_MGT5100)
88int board_early_init_r(void)
89{
90 /*
91 * Now, when we are in RAM, enable CS0
92 * because CS_BOOT cannot be written.
93 */
94 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
95 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
96
97 return 0;
98}
99#endif
100
101#ifdef CONFIG_PCI
102static struct pci_controller hose;
103
104extern void pci_mpc5xxx_init(struct pci_controller *);
105
106void pci_init_board(void)
107{
108 pci_mpc5xxx_init(&hose);
109}
110#endif
111
112#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
113
114/* IRDA_1 aka PSC6_3 (pin C13) */
115#define GPIO_IRDA_1 0x20000000UL
116
117void init_ide_reset (void)
118{
119 debug ("init_ide_reset\n");
120
121 /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
122 *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
123 *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1;
124}
125
126void ide_set_reset (int idereset)
127{
128 debug ("ide_reset(%d)\n", idereset);
129
130 if (idereset) {
131 *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
132 } else {
133 *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1;
134 }
135}
136#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
wdenk81050922004-07-11 20:04:51 +0000137
138#ifdef CONFIG_VIDEO_SED13806
139#include <sed13806.h>
140
141#define DISPLAY_WIDTH 640
142#define DISPLAY_HEIGHT 480
143
144#ifdef CONFIG_VIDEO_SED13806_8BPP
145#error CONFIG_VIDEO_SED13806_8BPP not supported.
146#endif /* CONFIG_VIDEO_SED13806_8BPP */
147
148#ifdef CONFIG_VIDEO_SED13806_16BPP
149static const S1D_REGS init_regs [] =
150{
151 {0x0001,0x00}, /* Miscellaneous Register */
152 {0x01FC,0x00}, /* Display Mode Register */
153 {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
154 {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
155 {0x0008,0x00}, /* General IO Pins Control Register 0 */
156 {0x0009,0x00}, /* General IO Pins Control Register 1 */
157 {0x0010,0x02}, /* Memory Clock Configuration Register */
158 {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
159 {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
160 {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
161 {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
162 {0x0021,0x03}, /* DRAM Refresh Rate Register */
163 {0x002A,0x00}, /* DRAM Timings Control Register 0 */
164 {0x002B,0x01}, /* DRAM Timings Control Register 1 */
165 {0x0020,0x80}, /* Memory Configuration Register */
166 {0x0030,0x25}, /* Panel Type Register */
167 {0x0031,0x00}, /* MOD Rate Register */
168 {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
169 {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
170 {0x0035,0x01}, /* TFT FPLINE Start Position Register */
171 {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
172 {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
173 {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
174 {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
175 {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
176 {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
177 {0x0040,0x05}, /* LCD Display Mode Register */
178 {0x0041,0x00}, /* LCD Miscellaneous Register */
179 {0x0042,0x00}, /* LCD Display Start Address Register 0 */
180 {0x0043,0x00}, /* LCD Display Start Address Register 1 */
181 {0x0044,0x00}, /* LCD Display Start Address Register 2 */
182 {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
183 {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
184 {0x0048,0x00}, /* LCD Pixel Panning Register */
185 {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
186 {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
187 {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
188 {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
189 {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
190 {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
191 {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
192 {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
193 {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
194 {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
195 {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
196 {0x005B,0x10}, /* TV Output Control Register */
197 {0x0060,0x05}, /* CRT/TV Display Mode Register */
198 {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
199 {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
200 {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
201 {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
202 {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
203 {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
204 {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
205 {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
206 {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
207 {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
208 {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
209 {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
210 {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
211 {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
212 {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
213 {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
214 {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
215 {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
216 {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
217 {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
218 {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
219 {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
220 {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
221 {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
222 {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
223 {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
224 {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
225 {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
226 {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
227 {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
228 {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
229 {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
230 {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
231 {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
232 {0x0100,0x00}, /* BitBlt Control Register 0 */
233 {0x0101,0x00}, /* BitBlt Control Register 1 */
234 {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
235 {0x0103,0x00}, /* BitBlt Operation Register */
236 {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
237 {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
238 {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
239 {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
240 {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
241 {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
242 {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
243 {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
244 {0x0110,0x00}, /* BitBlt Width Register 0 */
245 {0x0111,0x00}, /* BitBlt Width Register 1 */
246 {0x0112,0x00}, /* BitBlt Height Register 0 */
247 {0x0113,0x00}, /* BitBlt Height Register 1 */
248 {0x0114,0x00}, /* BitBlt Background Color Register 0 */
249 {0x0115,0x00}, /* BitBlt Background Color Register 1 */
250 {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
251 {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
252 {0x01E0,0x00}, /* Look-Up Table Mode Register */
253 {0x01E2,0x00}, /* Look-Up Table Address Register */
254 {0x01E4,0x00}, /* Look-Up Table Data Register */
255 {0x01F0,0x00}, /* Power Save Configuration Register */
256 {0x01F1,0x00}, /* Power Save Status Register */
257 {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
258 {0x01FC,0x01}, /* Display Mode Register */
259 {0, 0}
260};
261#endif /* CONFIG_VIDEO_SED13806_16BPP */
262
263#ifdef CONFIG_CONSOLE_EXTRA_INFO
264/* Return text to be printed besides the logo. */
265void video_get_info_str (int line_number, char *info)
266{
267 if (line_number == 1) {
wdenk281e00a2004-08-01 22:48:16 +0000268#ifdef CONFIG_MGT5100
wdenk81050922004-07-11 20:04:51 +0000269 strcpy (info, " Total5100");
270#elif CONFIG_TOTAL5200_REV==1
271 strcpy (info, " Total5200");
272#elif CONFIG_TOTAL5200_REV==2
273 strcpy (info, " Total5200 Rev.2");
274#else
275#error CONFIG_TOTAL5200_REV must be 1 or 2.
276#endif
277 } else {
278 info [0] = '\0';
279 }
280}
281#endif
282
283/* Returns SED13806 base address. First thing called in the driver. */
284unsigned int board_video_init (void)
285{
286 return CFG_LCD_BASE;
287}
288
289/* Called after initializing the SED13806 and before clearing the screen. */
290void board_validate_screen (unsigned int base)
291{
292}
293
294/* Return a pointer to the initialization sequence. */
295const S1D_REGS *board_get_regs (void)
296{
297 return init_regs;
298}
299
300int board_get_width (void)
301{
302 return DISPLAY_WIDTH;
303}
304
305int board_get_height (void)
306{
307 return DISPLAY_HEIGHT;
308}
309
310#endif /* CONFIG_VIDEO_SED13806 */