blob: af0e55cd2f2cd99e654d1484a66fdb761f3128d9 [file] [log] [blame]
Wilson Dinge51f2b12018-03-26 15:57:29 +08001/*
2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
17 */
18/* pcie_advk.c
19 *
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
21 *
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
Pali Rohár22f69fc2021-12-16 12:04:06 +010024 * Pali Rohár <pali@kernel.org>
Wilson Dinge51f2b12018-03-26 15:57:29 +080025 *
26 */
27
28#include <common.h>
29#include <dm.h>
30#include <pci.h>
31#include <asm/io.h>
32#include <asm-generic/gpio.h>
Simon Glass336d4612020-02-03 07:36:16 -070033#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060034#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060035#include <linux/delay.h>
Wilson Dinge51f2b12018-03-26 15:57:29 +080036#include <linux/ioport.h>
37
Pali Rohár819a43c2022-02-10 14:53:42 +010038/* PCIe Root Port register offsets */
39#define ADVK_ROOT_PORT_PCI_CFG_OFF 0x0
40#define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0
41#define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100
Wilson Dinge51f2b12018-03-26 15:57:29 +080042
Pali Rohárcf2a5892022-02-10 14:53:43 +010043/* PIO registers */
44#define ADVK_PIO_BASE_ADDR 0x4000
45#define ADVK_PIO_CTRL (ADVK_PIO_BASE_ADDR + 0x0)
46#define ADVK_PIO_CTRL_TYPE_MASK GENMASK(3, 0)
47#define ADVK_PIO_CTRL_TYPE_SHIFT 0
48#define ADVK_PIO_CTRL_TYPE_RD_TYPE0 0x8
49#define ADVK_PIO_CTRL_TYPE_RD_TYPE1 0x9
50#define ADVK_PIO_CTRL_TYPE_WR_TYPE0 0xa
51#define ADVK_PIO_CTRL_TYPE_WR_TYPE1 0xb
52#define ADVK_PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
53#define ADVK_PIO_STAT (ADVK_PIO_BASE_ADDR + 0x4)
54#define ADVK_PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
55#define ADVK_PIO_COMPLETION_STATUS_SHIFT 7
56#define ADVK_PIO_COMPLETION_STATUS_OK 0
57#define ADVK_PIO_COMPLETION_STATUS_UR 1
58#define ADVK_PIO_COMPLETION_STATUS_CRS 2
59#define ADVK_PIO_COMPLETION_STATUS_CA 4
60#define ADVK_PIO_NON_POSTED_REQ BIT(10)
61#define ADVK_PIO_ERR_STATUS BIT(11)
62#define ADVK_PIO_ADDR_LS (ADVK_PIO_BASE_ADDR + 0x8)
63#define ADVK_PIO_ADDR_MS (ADVK_PIO_BASE_ADDR + 0xc)
64#define ADVK_PIO_WR_DATA (ADVK_PIO_BASE_ADDR + 0x10)
65#define ADVK_PIO_WR_DATA_STRB (ADVK_PIO_BASE_ADDR + 0x14)
66#define ADVK_PIO_RD_DATA (ADVK_PIO_BASE_ADDR + 0x18)
67#define ADVK_PIO_START (ADVK_PIO_BASE_ADDR + 0x1c)
68#define ADVK_PIO_ISR (ADVK_PIO_BASE_ADDR + 0x20)
Wilson Dinge51f2b12018-03-26 15:57:29 +080069
Pali Rohárcf2a5892022-02-10 14:53:43 +010070/* Global Control registers */
71#define ADVK_GLOBAL_CTRL_BASE_ADDR 0x4800
72#define ADVK_GLOBAL_CTRL0 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x0)
73#define ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK GENMASK(1, 0)
74#define ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT 0
75#define ADVK_GLOBAL_CTRL0_SPEED_GEN_1 0
76#define ADVK_GLOBAL_CTRL0_SPEED_GEN_2 1
77#define ADVK_GLOBAL_CTRL0_SPEED_GEN_3 2
78#define ADVK_GLOBAL_CTRL0_IS_RC BIT(2)
79#define ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK GENMASK(4, 3)
80#define ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT 3
81#define ADVK_GLOBAL_CTRL0_LANE_COUNT_1 0
82#define ADVK_GLOBAL_CTRL0_LANE_COUNT_2 1
83#define ADVK_GLOBAL_CTRL0_LANE_COUNT_4 2
84#define ADVK_GLOBAL_CTRL0_LANE_COUNT_8 3
85#define ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN BIT(6)
86#define ADVK_GLOBAL_CTRL2 (ADVK_GLOBAL_CTRL_BASE_ADDR + 0x8)
87#define ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN BIT(5)
88#define ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN BIT(6)
Wilson Dinge51f2b12018-03-26 15:57:29 +080089
Pali Rohárcf2a5892022-02-10 14:53:43 +010090/* PCIe window configuration registers */
91#define ADVK_OB_WIN_BASE_ADDR 0x4c00
92#define ADVK_OB_WIN_BLOCK_SIZE 0x20
93#define ADVK_OB_WIN_COUNT 8
94#define ADVK_OB_WIN_REG_ADDR(win, offset) (ADVK_OB_WIN_BASE_ADDR + ADVK_OB_WIN_BLOCK_SIZE * (win) + (offset))
95#define ADVK_OB_WIN_MATCH_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x00)
96#define ADVK_OB_WIN_ENABLE BIT(0)
97#define ADVK_OB_WIN_MATCH_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x04)
98#define ADVK_OB_WIN_REMAP_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x08)
99#define ADVK_OB_WIN_REMAP_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x0c)
100#define ADVK_OB_WIN_MASK_LS(win) ADVK_OB_WIN_REG_ADDR(win, 0x10)
101#define ADVK_OB_WIN_MASK_MS(win) ADVK_OB_WIN_REG_ADDR(win, 0x14)
102#define ADVK_OB_WIN_ACTIONS(win) ADVK_OB_WIN_REG_ADDR(win, 0x18)
103#define ADVK_OB_WIN_DEFAULT_ACTIONS (ADVK_OB_WIN_ACTIONS(ADVK_OB_WIN_COUNT-1) + 0x4)
104#define ADVK_OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
105#define ADVK_OB_WIN_FUNC_NUM_SHIFT 24
106#define ADVK_OB_WIN_FUNC_NUM_ENABLE BIT(23)
107#define ADVK_OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
108#define ADVK_OB_WIN_BUS_NUM_BITS_SHIFT 20
109#define ADVK_OB_WIN_MSG_CODE_ENABLE BIT(22)
110#define ADVK_OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
111#define ADVK_OB_WIN_MSG_CODE_SHIFT 14
112#define ADVK_OB_WIN_MSG_PAYLOAD_LEN BIT(12)
113#define ADVK_OB_WIN_ATTR_ENABLE BIT(11)
114#define ADVK_OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
115#define ADVK_OB_WIN_ATTR_TC_SHIFT 8
116#define ADVK_OB_WIN_ATTR_RELAXED BIT(7)
117#define ADVK_OB_WIN_ATTR_NOSNOOP BIT(6)
118#define ADVK_OB_WIN_ATTR_POISON BIT(5)
119#define ADVK_OB_WIN_ATTR_IDO BIT(4)
120#define ADVK_OB_WIN_TYPE_MASK GENMASK(3, 0)
121#define ADVK_OB_WIN_TYPE_SHIFT 0
122#define ADVK_OB_WIN_TYPE_MEM 0x0
123#define ADVK_OB_WIN_TYPE_IO 0x4
124#define ADVK_OB_WIN_TYPE_CONFIG_TYPE0 0x8
125#define ADVK_OB_WIN_TYPE_CONFIG_TYPE1 0x9
126#define ADVK_OB_WIN_TYPE_MSG 0xc
Pali Rohárb3217222021-05-26 17:59:40 +0200127
Pali Rohárcf2a5892022-02-10 14:53:43 +0100128/* Local Management Interface registers */
129#define ADVK_LMI_BASE_ADDR 0x6000
130#define ADVK_LMI_PHY_CFG0 (ADVK_LMI_BASE_ADDR + 0x0)
131#define ADVK_LMI_PHY_CFG0_LTSSM_MASK GENMASK(29, 24)
132#define ADVK_LMI_PHY_CFG0_LTSSM_SHIFT 24
133#define ADVK_LMI_PHY_CFG0_LTSSM_L0 0x10
134#define ADVK_LMI_PHY_CFG0_LTSSM_DISABLED 0x20
135#define ADVK_LMI_VENDOR_ID (ADVK_LMI_BASE_ADDR + 0x44)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800136
Pali Rohárcf2a5892022-02-10 14:53:43 +0100137/* Core Control registers */
138#define ADVK_CORE_CTRL_BASE_ADDR 0x18000
139#define ADVK_CORE_CTRL_CONFIG (ADVK_CORE_CTRL_BASE_ADDR + 0x0)
140#define ADVK_CORE_CTRL_CONFIG_COMMAND_MODE BIT(0)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800141
Wilson Dinge51f2b12018-03-26 15:57:29 +0800142/* PCIe Retries & Timeout definitions */
Pali Roháreccbd4a2021-04-22 16:23:04 +0200143#define PIO_MAX_RETRIES 1500
144#define PIO_WAIT_TIMEOUT 1000
145#define LINK_MAX_RETRIES 10
Wilson Dinge51f2b12018-03-26 15:57:29 +0800146#define LINK_WAIT_TIMEOUT 100000
147
Pali Rohárcf2a5892022-02-10 14:53:43 +0100148#define CFG_RD_CRS_VAL 0xFFFF0001
Wilson Dinge51f2b12018-03-26 15:57:29 +0800149
Wilson Dinge51f2b12018-03-26 15:57:29 +0800150/**
151 * struct pcie_advk - Advk PCIe controller state
152 *
Marek Behún8247c902021-09-26 00:54:46 +0200153 * @base: The base address of the register space.
Marek Behún8247c902021-09-26 00:54:46 +0200154 * @sec_busno: Bus number for the device behind the PCIe root-port.
155 * @dev: The pointer to PCI uclass device.
156 * @reset_gpio: GPIO descriptor for PERST.
157 * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers
158 * that are not available on Aardvark.
159 * @cfgcrssve: For CRSSVE emulation.
Wilson Dinge51f2b12018-03-26 15:57:29 +0800160 */
161struct pcie_advk {
Marek Behún96a3c982021-09-26 00:54:45 +0200162 void *base;
Marek Behún96a3c982021-09-26 00:54:45 +0200163 int sec_busno;
164 struct udevice *dev;
165 struct gpio_desc reset_gpio;
Pali Rohárfed5bec2021-11-11 16:35:48 +0100166 u32 cfgcache[(0x3c - 0x10) / 4];
Marek Behún96a3c982021-09-26 00:54:45 +0200167 bool cfgcrssve;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800168};
169
170static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
171{
172 writel(val, pcie->base + reg);
173}
174
175static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
176{
177 return readl(pcie->base + reg);
178}
179
180/**
Pali Rohár2727e9d2022-02-15 11:23:35 +0100181 * pcie_advk_link_up() - Check if PCIe link is up or not
182 *
183 * @pcie: The PCI device to access
184 *
185 * Return true on link up.
186 * Return false on link down.
187 */
188static bool pcie_advk_link_up(struct pcie_advk *pcie)
189{
190 u32 val, ltssm_state;
191
192 val = advk_readl(pcie, ADVK_LMI_PHY_CFG0);
193 ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT;
194 return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED;
195}
196
197/**
Wilson Dinge51f2b12018-03-26 15:57:29 +0800198 * pcie_advk_addr_valid() - Check for valid bus address
199 *
Pali Rohárcb056002021-09-26 00:54:42 +0200200 * @pcie: Pointer to the PCI bus
201 * @busno: Bus number of PCI device
202 * @dev: Device number of PCI device
203 * @func: Function number of PCI device
Wilson Dinge51f2b12018-03-26 15:57:29 +0800204 * @bdf: The PCI device to access
Wilson Dinge51f2b12018-03-26 15:57:29 +0800205 *
Pali Rohárcb056002021-09-26 00:54:42 +0200206 * Return: true on valid, false on invalid
Wilson Dinge51f2b12018-03-26 15:57:29 +0800207 */
Pali Rohárcb056002021-09-26 00:54:42 +0200208static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
209 int busno, u8 dev, u8 func)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800210{
Pali Rohár2a9059a2022-02-10 14:53:45 +0100211 /* On the root bus there is only one PCI Bridge */
212 if (busno == 0 && (dev != 0 || func != 0))
Pali Rohárcb056002021-09-26 00:54:42 +0200213 return false;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800214
Pali Rohár2727e9d2022-02-15 11:23:35 +0100215 /* Access to other buses is possible when link is up */
216 if (busno != 0 && !pcie_advk_link_up(pcie))
217 return false;
218
Pali Rohárcb056002021-09-26 00:54:42 +0200219 /*
220 * In PCI-E only a single device (0) can exist on the secondary bus.
221 * Beyond the secondary bus, there might be a Switch and anything is
222 * possible.
223 */
224 if (busno == pcie->sec_busno && dev != 0)
225 return false;
226
227 return true;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800228}
229
230/**
231 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
232 *
233 * @pcie: The PCI device to access
234 *
Pali Roháreccbd4a2021-04-22 16:23:04 +0200235 * Wait up to 1.5 seconds for PIO access to be accomplished.
Wilson Dinge51f2b12018-03-26 15:57:29 +0800236 *
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200237 * Return positive - retry count if PIO access is accomplished.
238 * Return negative - error if PIO access is timed out.
Wilson Dinge51f2b12018-03-26 15:57:29 +0800239 */
240static int pcie_advk_wait_pio(struct pcie_advk *pcie)
241{
242 uint start, isr;
243 uint count;
244
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200245 for (count = 1; count <= PIO_MAX_RETRIES; count++) {
Pali Rohárcf2a5892022-02-10 14:53:43 +0100246 start = advk_readl(pcie, ADVK_PIO_START);
247 isr = advk_readl(pcie, ADVK_PIO_ISR);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800248 if (!start && isr)
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200249 return count;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800250 /*
251 * Do not check the PIO state too frequently,
252 * 100us delay is appropriate.
253 */
254 udelay(PIO_WAIT_TIMEOUT);
255 }
256
Pali Roháreccbd4a2021-04-22 16:23:04 +0200257 dev_err(pcie->dev, "PIO read/write transfer time out\n");
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200258 return -ETIMEDOUT;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800259}
260
261/**
262 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
263 *
264 * @pcie: Pointer to the PCI bus
Pali Rohár4cd61c42021-08-09 09:53:13 +0200265 * @allow_crs: Only for read requests, if CRS response is allowed
266 * @read_val: Pointer to the read result
Wilson Dinge51f2b12018-03-26 15:57:29 +0800267 *
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200268 * Return: 0 on success
Wilson Dinge51f2b12018-03-26 15:57:29 +0800269 */
270static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
Pali Rohár4cd61c42021-08-09 09:53:13 +0200271 bool allow_crs,
Wilson Dinge51f2b12018-03-26 15:57:29 +0800272 uint *read_val)
273{
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200274 int ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800275 uint reg;
276 unsigned int status;
277 char *strcomp_status, *str_posted;
278
Pali Rohárcf2a5892022-02-10 14:53:43 +0100279 reg = advk_readl(pcie, ADVK_PIO_STAT);
280 status = (reg & ADVK_PIO_COMPLETION_STATUS_MASK) >>
281 ADVK_PIO_COMPLETION_STATUS_SHIFT;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800282
283 switch (status) {
Pali Rohárcf2a5892022-02-10 14:53:43 +0100284 case ADVK_PIO_COMPLETION_STATUS_OK:
285 if (reg & ADVK_PIO_ERR_STATUS) {
Wilson Dinge51f2b12018-03-26 15:57:29 +0800286 strcomp_status = "COMP_ERR";
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200287 ret = -EFAULT;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800288 break;
289 }
290 /* Get the read result */
Pali Rohár4cd61c42021-08-09 09:53:13 +0200291 if (read_val)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100292 *read_val = advk_readl(pcie, ADVK_PIO_RD_DATA);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800293 /* No error */
294 strcomp_status = NULL;
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200295 ret = 0;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800296 break;
Pali Rohárcf2a5892022-02-10 14:53:43 +0100297 case ADVK_PIO_COMPLETION_STATUS_UR:
Pali Rohár4cd61c42021-08-09 09:53:13 +0200298 strcomp_status = "UR";
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200299 ret = -EOPNOTSUPP;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800300 break;
Pali Rohárcf2a5892022-02-10 14:53:43 +0100301 case ADVK_PIO_COMPLETION_STATUS_CRS:
Pali Rohár4cd61c42021-08-09 09:53:13 +0200302 if (allow_crs && read_val) {
Wilson Dinge51f2b12018-03-26 15:57:29 +0800303 /* For reading, CRS is not an error status. */
304 *read_val = CFG_RD_CRS_VAL;
305 strcomp_status = NULL;
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200306 ret = 0;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800307 } else {
308 strcomp_status = "CRS";
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200309 ret = -EAGAIN;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800310 }
311 break;
Pali Rohárcf2a5892022-02-10 14:53:43 +0100312 case ADVK_PIO_COMPLETION_STATUS_CA:
Wilson Dinge51f2b12018-03-26 15:57:29 +0800313 strcomp_status = "CA";
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200314 ret = -ECANCELED;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800315 break;
316 default:
317 strcomp_status = "Unknown";
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200318 ret = -EINVAL;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800319 break;
320 }
321
322 if (!strcomp_status)
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200323 return ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800324
Pali Rohárcf2a5892022-02-10 14:53:43 +0100325 if (reg & ADVK_PIO_NON_POSTED_REQ)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800326 str_posted = "Non-posted";
327 else
328 str_posted = "Posted";
329
Marek Behún157bc522021-09-07 17:27:08 +0200330 dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
Wilson Dinge51f2b12018-03-26 15:57:29 +0800331 str_posted, strcomp_status, reg,
Pali Rohárcf2a5892022-02-10 14:53:43 +0100332 advk_readl(pcie, ADVK_PIO_ADDR_LS));
Wilson Dinge51f2b12018-03-26 15:57:29 +0800333
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200334 return ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800335}
336
337/**
338 * pcie_advk_read_config() - Read from configuration space
339 *
340 * @bus: Pointer to the PCI bus
341 * @bdf: Identifies the PCIe device to access
342 * @offset: The offset into the device's configuration space
343 * @valuep: A pointer at which to store the read value
344 * @size: Indicates the size of access to perform
345 *
346 * Read a value of size @size from offset @offset within the configuration
347 * space of the device identified by the bus, device & function numbers in @bdf
348 * on the PCI bus @bus.
349 *
350 * Return: 0 on success
351 */
Simon Glassc4e72c42020-01-27 08:49:37 -0700352static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
Wilson Dinge51f2b12018-03-26 15:57:29 +0800353 uint offset, ulong *valuep,
354 enum pci_size_t size)
355{
356 struct pcie_advk *pcie = dev_get_priv(bus);
Pali Rohárcb056002021-09-26 00:54:42 +0200357 int busno = PCI_BUS(bdf) - dev_seq(bus);
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200358 int retry_count;
Pali Rohár4cd61c42021-08-09 09:53:13 +0200359 bool allow_crs;
Pali Rohárcb056002021-09-26 00:54:42 +0200360 ulong data;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800361 uint reg;
362 int ret;
363
364 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
365 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
366
Pali Rohárcb056002021-09-26 00:54:42 +0200367 if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
Wilson Dinge51f2b12018-03-26 15:57:29 +0800368 dev_dbg(pcie->dev, "- out of range\n");
369 *valuep = pci_get_ff(size);
370 return 0;
371 }
372
Pali Rohár758262b2021-08-27 14:14:43 +0200373 /*
Pali Rohár2a9059a2022-02-10 14:53:45 +0100374 * The configuration space of the PCI Bridge on the root bus (zero) is
Pali Rohárcb056002021-09-26 00:54:42 +0200375 * not accessible via PIO transfers like all other PCIe devices. PCI
376 * Bridge config registers are available directly in Aardvark memory
Pali Rohárfed5bec2021-11-11 16:35:48 +0100377 * space starting at offset zero. The PCI Bridge config space is of
378 * Type 0, but the BAR registers (including ROM BAR) don't have the same
379 * meaning as in the PCIe specification. Therefore do not access BAR
380 * registers and non-common registers (those which have different
Pali Rohár2a9059a2022-02-10 14:53:45 +0100381 * meaning for Type 0 and Type 1 config space) of the PCI Bridge
Pali Rohárfed5bec2021-11-11 16:35:48 +0100382 * and instead read their content from driver virtual cfgcache[].
Pali Rohárcb056002021-09-26 00:54:42 +0200383 */
Pali Rohár2a9059a2022-02-10 14:53:45 +0100384 if (busno == 0) {
Pali Rohárfed5bec2021-11-11 16:35:48 +0100385 if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c))
Pali Rohárcb056002021-09-26 00:54:42 +0200386 data = pcie->cfgcache[(offset - 0x10) / 4];
Pali Rohárcb056002021-09-26 00:54:42 +0200387 else
Pali Rohár819a43c2022-02-10 14:53:42 +0100388 data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
Pali Rohárcb056002021-09-26 00:54:42 +0200389
390 if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
391 /*
392 * Change Header Type of PCI Bridge device to Type 1
393 * (0x01, used by PCI Bridges) because hardwired value
394 * is Type 0 (0x00, used by Endpoint devices).
395 */
396 data &= ~0x007f0000;
397 data |= PCI_HEADER_TYPE_BRIDGE << 16;
398 }
399
Pali Rohár819a43c2022-02-10 14:53:42 +0100400 if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) {
Pali Rohár1d7ad682021-09-26 00:54:44 +0200401 /* CRSSVE bit is stored only in cache */
402 if (pcie->cfgcrssve)
403 data |= PCI_EXP_RTCTL_CRSSVE;
404 }
405
Pali Rohár819a43c2022-02-10 14:53:42 +0100406 if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + (PCI_EXP_RTCAP & ~3)) {
Pali Rohár1d7ad682021-09-26 00:54:44 +0200407 /* CRS is emulated below, so set CRSVIS capability */
408 data |= PCI_EXP_RTCAP_CRSVIS << 16;
409 }
410
Pali Rohárcb056002021-09-26 00:54:42 +0200411 *valuep = pci_conv_32_to_size(data, offset, size);
412
413 return 0;
414 }
415
416 /*
Pali Rohár758262b2021-08-27 14:14:43 +0200417 * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
418 * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
419 * only when CRSSVE bit in Root Port PCIe device is enabled. In all
420 * other error PCIe Root Complex must return all-ones.
Pali Rohár1d7ad682021-09-26 00:54:44 +0200421 *
Pali Rohár758262b2021-08-27 14:14:43 +0200422 * U-Boot currently does not support handling of CRS return value for
423 * PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
Pali Rohár1d7ad682021-09-26 00:54:44 +0200424 * So it means that pcie->cfgcrssve is false. But the code is prepared
425 * for returning CRS, so that if U-Boot does support CRS in the future,
426 * it will work for Aardvark.
Pali Rohár758262b2021-08-27 14:14:43 +0200427 */
Pali Rohárbd4064f2021-10-19 11:05:01 +0200428 allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
Pali Rohár4cd61c42021-08-09 09:53:13 +0200429
Pali Rohárcf2a5892022-02-10 14:53:43 +0100430 if (advk_readl(pcie, ADVK_PIO_START)) {
Pali Roháreccbd4a2021-04-22 16:23:04 +0200431 dev_err(pcie->dev,
432 "Previous PIO read/write transfer is still running\n");
Pali Rohár4cd61c42021-08-09 09:53:13 +0200433 if (allow_crs) {
434 *valuep = CFG_RD_CRS_VAL;
435 return 0;
436 }
437 *valuep = pci_get_ff(size);
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200438 return -EAGAIN;
Pali Roháreccbd4a2021-04-22 16:23:04 +0200439 }
Wilson Dinge51f2b12018-03-26 15:57:29 +0800440
441 /* Program the control register */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100442 reg = advk_readl(pcie, ADVK_PIO_CTRL);
443 reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
Pali Rohárcb056002021-09-26 00:54:42 +0200444 if (busno == pcie->sec_busno)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100445 reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800446 else
Pali Rohárcf2a5892022-02-10 14:53:43 +0100447 reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
448 advk_writel(pcie, reg, ADVK_PIO_CTRL);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800449
450 /* Program the address registers */
Pali Rohára4bc38d2021-11-03 01:01:05 +0100451 reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
Pali Rohárcf2a5892022-02-10 14:53:43 +0100452 advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
453 advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800454
Pali Rohár57fa6fb2021-11-01 10:12:51 +0100455 /* Program the data strobe */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100456 advk_writel(pcie, 0xf, ADVK_PIO_WR_DATA_STRB);
Pali Rohár57fa6fb2021-11-01 10:12:51 +0100457
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200458 retry_count = 0;
459
460retry:
Wilson Dinge51f2b12018-03-26 15:57:29 +0800461 /* Start the transfer */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100462 advk_writel(pcie, 1, ADVK_PIO_ISR);
463 advk_writel(pcie, 1, ADVK_PIO_START);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800464
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200465 ret = pcie_advk_wait_pio(pcie);
466 if (ret < 0) {
Pali Rohár4cd61c42021-08-09 09:53:13 +0200467 if (allow_crs) {
468 *valuep = CFG_RD_CRS_VAL;
469 return 0;
470 }
471 *valuep = pci_get_ff(size);
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200472 return ret;
Pali Roháreccbd4a2021-04-22 16:23:04 +0200473 }
Wilson Dinge51f2b12018-03-26 15:57:29 +0800474
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200475 retry_count += ret;
476
Wilson Dinge51f2b12018-03-26 15:57:29 +0800477 /* Check PIO status and get the read result */
Pali Rohár4cd61c42021-08-09 09:53:13 +0200478 ret = pcie_advk_check_pio_status(pcie, allow_crs, &reg);
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200479 if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
480 goto retry;
Pali Rohár4cd61c42021-08-09 09:53:13 +0200481 if (ret) {
482 *valuep = pci_get_ff(size);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800483 return ret;
Pali Rohár4cd61c42021-08-09 09:53:13 +0200484 }
Wilson Dinge51f2b12018-03-26 15:57:29 +0800485
486 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
487 offset, size, reg);
488 *valuep = pci_conv_32_to_size(reg, offset, size);
489
490 return 0;
491}
492
493/**
494 * pcie_calc_datastrobe() - Calculate data strobe
495 *
496 * @offset: The offset into the device's configuration space
497 * @size: Indicates the size of access to perform
498 *
499 * Calculate data strobe according to offset and size
500 *
501 */
502static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
503{
504 uint bytes, data_strobe;
505
506 switch (size) {
507 case PCI_SIZE_8:
508 bytes = 1;
509 break;
510 case PCI_SIZE_16:
511 bytes = 2;
512 break;
513 default:
514 bytes = 4;
515 }
516
517 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
518
519 return data_strobe;
520}
521
522/**
523 * pcie_advk_write_config() - Write to configuration space
524 *
525 * @bus: Pointer to the PCI bus
526 * @bdf: Identifies the PCIe device to access
527 * @offset: The offset into the device's configuration space
528 * @value: The value to write
529 * @size: Indicates the size of access to perform
530 *
531 * Write the value @value of size @size from offset @offset within the
532 * configuration space of the device identified by the bus, device & function
533 * numbers in @bdf on the PCI bus @bus.
534 *
535 * Return: 0 on success
536 */
537static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
538 uint offset, ulong value,
539 enum pci_size_t size)
540{
541 struct pcie_advk *pcie = dev_get_priv(bus);
Pali Rohárcb056002021-09-26 00:54:42 +0200542 int busno = PCI_BUS(bdf) - dev_seq(bus);
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200543 int retry_count;
Pali Rohárcb056002021-09-26 00:54:42 +0200544 ulong data;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800545 uint reg;
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200546 int ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800547
548 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
549 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
550 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
551 offset, size, value);
552
Pali Rohárcb056002021-09-26 00:54:42 +0200553 if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
Wilson Dinge51f2b12018-03-26 15:57:29 +0800554 dev_dbg(pcie->dev, "- out of range\n");
555 return 0;
556 }
557
Pali Rohárcb056002021-09-26 00:54:42 +0200558 /*
Pali Rohárfed5bec2021-11-11 16:35:48 +0100559 * As explained in pcie_advk_read_config(), PCI Bridge config registers
560 * are available directly in Aardvark memory space starting at offset
561 * zero. Type 1 specific registers are not available, so we write their
562 * content only into driver virtual cfgcache[].
Pali Rohárcb056002021-09-26 00:54:42 +0200563 */
Pali Rohár2a9059a2022-02-10 14:53:45 +0100564 if (busno == 0) {
Pali Rohárfed5bec2021-11-11 16:35:48 +0100565 if ((offset >= 0x10 && offset < 0x34) ||
566 (offset >= 0x38 && offset < 0x3c)) {
Pali Rohárcb056002021-09-26 00:54:42 +0200567 data = pcie->cfgcache[(offset - 0x10) / 4];
568 data = pci_conv_size_to_32(data, value, offset, size);
Pali Roháraaddce02021-10-12 13:19:19 +0200569 /* This PCI bridge does not have configurable bars */
570 if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
Pali Rohárfed5bec2021-11-11 16:35:48 +0100571 (offset & ~3) == PCI_BASE_ADDRESS_1 ||
572 (offset & ~3) == PCI_ROM_ADDRESS1)
Pali Roháraaddce02021-10-12 13:19:19 +0200573 data = 0x0;
Pali Rohárcb056002021-09-26 00:54:42 +0200574 pcie->cfgcache[(offset - 0x10) / 4] = data;
Pali Rohárcb056002021-09-26 00:54:42 +0200575 } else {
Pali Rohár819a43c2022-02-10 14:53:42 +0100576 data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
Pali Rohárcb056002021-09-26 00:54:42 +0200577 data = pci_conv_size_to_32(data, value, offset, size);
Pali Rohár819a43c2022-02-10 14:53:42 +0100578 advk_writel(pcie, data, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
Pali Rohárcb056002021-09-26 00:54:42 +0200579 }
580
Pali Rohárcb056002021-09-26 00:54:42 +0200581 if (offset == PCI_SECONDARY_BUS ||
582 (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
583 pcie->sec_busno = (data >> 8) & 0xff;
584
Pali Rohár819a43c2022-02-10 14:53:42 +0100585 if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL)
Pali Rohár1d7ad682021-09-26 00:54:44 +0200586 pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
587
Pali Rohárcb056002021-09-26 00:54:42 +0200588 return 0;
589 }
590
Pali Rohárcf2a5892022-02-10 14:53:43 +0100591 if (advk_readl(pcie, ADVK_PIO_START)) {
Pali Roháreccbd4a2021-04-22 16:23:04 +0200592 dev_err(pcie->dev,
593 "Previous PIO read/write transfer is still running\n");
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200594 return -EAGAIN;
Pali Roháreccbd4a2021-04-22 16:23:04 +0200595 }
Wilson Dinge51f2b12018-03-26 15:57:29 +0800596
597 /* Program the control register */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100598 reg = advk_readl(pcie, ADVK_PIO_CTRL);
599 reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
Pali Rohárcb056002021-09-26 00:54:42 +0200600 if (busno == pcie->sec_busno)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100601 reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800602 else
Pali Rohárcf2a5892022-02-10 14:53:43 +0100603 reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
604 advk_writel(pcie, reg, ADVK_PIO_CTRL);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800605
606 /* Program the address registers */
Pali Rohára4bc38d2021-11-03 01:01:05 +0100607 reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
Pali Rohárcf2a5892022-02-10 14:53:43 +0100608 advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
609 advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800610 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
611
612 /* Program the data register */
613 reg = pci_conv_size_to_32(0, value, offset, size);
Pali Rohárcf2a5892022-02-10 14:53:43 +0100614 advk_writel(pcie, reg, ADVK_PIO_WR_DATA);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800615 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
616
617 /* Program the data strobe */
618 reg = pcie_calc_datastrobe(offset, size);
Pali Rohárcf2a5892022-02-10 14:53:43 +0100619 advk_writel(pcie, reg, ADVK_PIO_WR_DATA_STRB);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800620 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
621
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200622 retry_count = 0;
623
624retry:
Wilson Dinge51f2b12018-03-26 15:57:29 +0800625 /* Start the transfer */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100626 advk_writel(pcie, 1, ADVK_PIO_ISR);
627 advk_writel(pcie, 1, ADVK_PIO_START);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800628
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200629 ret = pcie_advk_wait_pio(pcie);
630 if (ret < 0)
631 return ret;
632
633 retry_count += ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800634
635 /* Check PIO status */
Pali Rohárd9ac6e22021-08-27 14:14:44 +0200636 ret = pcie_advk_check_pio_status(pcie, false, NULL);
637 if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
638 goto retry;
639 return ret;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800640}
641
642/**
Wilson Dinge51f2b12018-03-26 15:57:29 +0800643 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
644 *
645 * @pcie: The PCI device to access
646 *
647 * Wait up to 1 second for link training to be accomplished.
Wilson Dinge51f2b12018-03-26 15:57:29 +0800648 */
Pali Rohár6c7ccb92022-02-15 11:23:36 +0100649static void pcie_advk_wait_for_link(struct pcie_advk *pcie)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800650{
651 int retries;
652
653 /* check if the link is up or not */
Pali Roháreccbd4a2021-04-22 16:23:04 +0200654 for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
Wilson Dinge51f2b12018-03-26 15:57:29 +0800655 if (pcie_advk_link_up(pcie)) {
Pali Rohárcb056002021-09-26 00:54:42 +0200656 printf("PCIe: Link up\n");
Pali Rohár6c7ccb92022-02-15 11:23:36 +0100657 return;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800658 }
659
660 udelay(LINK_WAIT_TIMEOUT);
661 }
662
Pali Rohárcb056002021-09-26 00:54:42 +0200663 printf("PCIe: Link down\n");
Wilson Dinge51f2b12018-03-26 15:57:29 +0800664}
665
Pali Rohárb3217222021-05-26 17:59:40 +0200666/*
667 * Set PCIe address window register which could be used for memory
668 * mapping.
669 */
670static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
671 phys_addr_t match, phys_addr_t remap,
672 phys_addr_t mask, u32 actions)
673{
Pali Rohárcf2a5892022-02-10 14:53:43 +0100674 advk_writel(pcie, ADVK_OB_WIN_ENABLE |
675 lower_32_bits(match), ADVK_OB_WIN_MATCH_LS(win_num));
676 advk_writel(pcie, upper_32_bits(match), ADVK_OB_WIN_MATCH_MS(win_num));
677 advk_writel(pcie, lower_32_bits(remap), ADVK_OB_WIN_REMAP_LS(win_num));
678 advk_writel(pcie, upper_32_bits(remap), ADVK_OB_WIN_REMAP_MS(win_num));
679 advk_writel(pcie, lower_32_bits(mask), ADVK_OB_WIN_MASK_LS(win_num));
680 advk_writel(pcie, upper_32_bits(mask), ADVK_OB_WIN_MASK_MS(win_num));
681 advk_writel(pcie, actions, ADVK_OB_WIN_ACTIONS(win_num));
Pali Rohárb3217222021-05-26 17:59:40 +0200682}
683
684static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
685{
Pali Rohárcf2a5892022-02-10 14:53:43 +0100686 advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_LS(win_num));
687 advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_MS(win_num));
688 advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_LS(win_num));
689 advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_MS(win_num));
690 advk_writel(pcie, 0, ADVK_OB_WIN_MASK_LS(win_num));
691 advk_writel(pcie, 0, ADVK_OB_WIN_MASK_MS(win_num));
692 advk_writel(pcie, 0, ADVK_OB_WIN_ACTIONS(win_num));
Pali Rohárb3217222021-05-26 17:59:40 +0200693}
694
695static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
696 struct pci_region *region, u32 actions)
697{
698 phys_addr_t phys_start = region->phys_start;
699 pci_addr_t bus_start = region->bus_start;
700 pci_size_t size = region->size;
701 phys_addr_t win_mask;
702 u64 win_size;
703
704 if (*wins == -1)
705 return;
706
707 /*
708 * The n-th PCIe window is configured by tuple (match, remap, mask)
Pali Rohár960d4592021-07-08 20:19:00 +0200709 * and an access to address A uses this window if A matches the
Pali Rohárb3217222021-05-26 17:59:40 +0200710 * match with given mask.
711 * So every PCIe window size must be a power of two and every start
712 * address must be aligned to window size. Minimal size is 64 KiB
Pali Rohára8314952021-07-08 20:18:58 +0200713 * because lower 16 bits of mask must be zero. Remapped address
714 * may have set only bits from the mask.
Pali Rohárb3217222021-05-26 17:59:40 +0200715 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100716 while (*wins < ADVK_OB_WIN_COUNT && size > 0) {
Pali Rohárb3217222021-05-26 17:59:40 +0200717 /* Calculate the largest aligned window size */
718 win_size = (1ULL << (fls64(size) - 1)) |
719 (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
720 win_size = 1ULL << __ffs64(win_size);
Pali Rohára8314952021-07-08 20:18:58 +0200721 win_mask = ~(win_size - 1);
722 if (win_size < 0x10000 || (bus_start & ~win_mask))
Pali Rohárb3217222021-05-26 17:59:40 +0200723 break;
724
725 dev_dbg(pcie->dev,
726 "Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
727 *wins, (u64)phys_start, (u64)phys_start + win_size,
728 actions);
Pali Rohárb3217222021-05-26 17:59:40 +0200729 pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
730 win_mask, actions);
731
732 phys_start += win_size;
733 bus_start += win_size;
734 size -= win_size;
735 (*wins)++;
736 }
737
738 if (size > 0) {
739 *wins = -1;
740 dev_err(pcie->dev,
741 "Invalid PCIe region [0x%llx-0x%llx]\n",
742 (u64)region->phys_start,
743 (u64)region->phys_start + region->size);
744 }
745}
746
Wilson Dinge51f2b12018-03-26 15:57:29 +0800747/**
748 * pcie_advk_setup_hw() - PCIe initailzation
749 *
750 * @pcie: The PCI device to access
751 *
752 * Return: 0 on success
753 */
754static int pcie_advk_setup_hw(struct pcie_advk *pcie)
755{
Pali Rohárb3217222021-05-26 17:59:40 +0200756 struct pci_region *io, *mem, *pref;
757 int i, wins;
Wilson Dinge51f2b12018-03-26 15:57:29 +0800758 u32 reg;
759
Pali Rohár682bad82022-02-15 11:23:37 +0100760 /* Set from Command to Direct mode */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100761 reg = advk_readl(pcie, ADVK_CORE_CTRL_CONFIG);
762 reg &= ~ADVK_CORE_CTRL_CONFIG_COMMAND_MODE;
763 advk_writel(pcie, reg, ADVK_CORE_CTRL_CONFIG);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800764
765 /* Set PCI global control register to RC mode */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100766 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
767 reg |= ADVK_GLOBAL_CTRL0_IS_RC;
768 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800769
Pali Rohár2fa30d02021-03-03 14:37:59 +0100770 /*
771 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
Pali Rohárcf2a5892022-02-10 14:53:43 +0100772 * ADVK_LMI_VENDOR_ID contains vendor id in low 16 bits and subsystem vendor
Pali Rohár2fa30d02021-03-03 14:37:59 +0100773 * id in high 16 bits. Updating this register changes readback value of
Pali Rohárcf2a5892022-02-10 14:53:43 +0100774 * read-only vendor id bits in Root Port PCI_VENDOR_ID register. Workaround
Pali Rohár2fa30d02021-03-03 14:37:59 +0100775 * for erratum 4.1: "The value of device and vendor ID is incorrect".
776 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100777 advk_writel(pcie, 0x11ab11ab, ADVK_LMI_VENDOR_ID);
Pali Rohár2fa30d02021-03-03 14:37:59 +0100778
Pali Rohárcb056002021-09-26 00:54:42 +0200779 /*
780 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
781 * because default value is Mass Storage Controller (0x010400), causing
782 * U-Boot to fail to recognize it as P2P Bridge.
783 *
784 * Note that this Aardvark PCI Bridge does not have a compliant Type 1
785 * Configuration Space and it even cannot be accessed via Aardvark's
Pali Rohárfed5bec2021-11-11 16:35:48 +0100786 * PCI config space access method. Aardvark PCI Bridge Config space is
Pali Rohárcb056002021-09-26 00:54:42 +0200787 * available in internal Aardvark registers starting at offset 0x0
Pali Rohárfed5bec2021-11-11 16:35:48 +0100788 * and has format of Type 0 config space.
789 *
790 * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
791 * have the same format in Marvell's specification as in PCIe
792 * specification, but their meaning is totally different (and not even
793 * the same meaning as explained in the corresponding comment in the
794 * pci_mvebu driver; aardvark is still different).
795 *
796 * So our driver converts Type 0 config space to Type 1 and reports
797 * Header Type as Type 1. Access to BAR registers and to non-existent
798 * Type 1 registers is redirected to the virtual cfgcache[] buffer,
799 * which avoids changing unrelated registers.
Pali Rohárcb056002021-09-26 00:54:42 +0200800 */
Pali Rohár819a43c2022-02-10 14:53:42 +0100801 reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
Pali Rohárcb056002021-09-26 00:54:42 +0200802 reg &= ~0xffffff00;
Pali Rohárd7b90402022-02-18 13:18:40 +0100803 reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
Pali Rohár819a43c2022-02-10 14:53:42 +0100804 advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
Pali Rohárcb056002021-09-26 00:54:42 +0200805
Pali Rohár819a43c2022-02-10 14:53:42 +0100806 /* Enable generation and checking of ECRC on PCIe Root Port */
807 reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
808 reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
809 advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800810
Pali Rohár819a43c2022-02-10 14:53:42 +0100811 /* Set PCIe Device Control register on PCIe Root Port */
812 reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
813 reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
814 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
815 reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
816 reg &= ~PCI_EXP_DEVCTL_READRQ;
817 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
818 reg |= PCI_EXP_DEVCTL_READRQ_512B;
819 advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800820
821 /* Program PCIe Control 2 to disable strict ordering */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100822 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
823 reg &= ~ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN;
824 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800825
826 /* Set GEN2 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100827 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
828 reg &= ~ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK;
829 reg |= ADVK_GLOBAL_CTRL0_SPEED_GEN_2 << ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT;
830 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800831
832 /* Set lane X1 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100833 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
834 reg &= ~ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK;
835 reg |= ADVK_GLOBAL_CTRL0_LANE_COUNT_1 << ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT;
836 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800837
838 /* Enable link training */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100839 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
840 reg |= ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
841 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800842
843 /*
844 * Enable AXI address window location generation:
845 * When it is enabled, the default outbound window
846 * configurations (Default User Field: 0xD0074CFC)
847 * are used to transparent address translation for
848 * the outbound transactions. Thus, PCIe address
Pali Rohárb3217222021-05-26 17:59:40 +0200849 * windows are not required for transparent memory
850 * access when default outbound window configuration
851 * is set for memory access.
Wilson Dinge51f2b12018-03-26 15:57:29 +0800852 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100853 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
854 reg |= ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN;
855 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800856
857 /*
858 * Bypass the address window mapping for PIO:
859 * Since PIO access already contains all required
860 * info over AXI interface by PIO registers, the
861 * address window is not required.
862 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100863 reg = advk_readl(pcie, ADVK_PIO_CTRL);
864 reg |= ADVK_PIO_CTRL_ADDR_WIN_DISABLE;
865 advk_writel(pcie, reg, ADVK_PIO_CTRL);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800866
Pali Rohárb3217222021-05-26 17:59:40 +0200867 /*
868 * Set memory access in Default User Field so it
869 * is not required to configure PCIe address for
870 * transparent memory access.
871 */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100872 advk_writel(pcie, ADVK_OB_WIN_TYPE_MEM, ADVK_OB_WIN_DEFAULT_ACTIONS);
Pali Rohárb3217222021-05-26 17:59:40 +0200873
874 /*
875 * Configure PCIe address windows for non-memory or
876 * non-transparent access as by default PCIe uses
877 * transparent memory access.
878 */
879 wins = 0;
880 pci_get_regions(pcie->dev, &io, &mem, &pref);
881 if (io)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100882 pcie_advk_set_ob_region(pcie, &wins, io, ADVK_OB_WIN_TYPE_IO);
Pali Rohárb3217222021-05-26 17:59:40 +0200883 if (mem && mem->phys_start != mem->bus_start)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100884 pcie_advk_set_ob_region(pcie, &wins, mem, ADVK_OB_WIN_TYPE_MEM);
Pali Rohárb3217222021-05-26 17:59:40 +0200885 if (pref && pref->phys_start != pref->bus_start)
Pali Rohárcf2a5892022-02-10 14:53:43 +0100886 pcie_advk_set_ob_region(pcie, &wins, pref, ADVK_OB_WIN_TYPE_MEM);
Pali Rohárb3217222021-05-26 17:59:40 +0200887
888 /* Disable remaining PCIe outbound windows */
Pali Rohárcf2a5892022-02-10 14:53:43 +0100889 for (i = ((wins >= 0) ? wins : 0); i < ADVK_OB_WIN_COUNT; i++)
Pali Rohárb3217222021-05-26 17:59:40 +0200890 pcie_advk_disable_ob_win(pcie, i);
891
892 if (wins == -1)
893 return -EINVAL;
894
Wilson Dinge51f2b12018-03-26 15:57:29 +0800895 /* Wait for PCIe link up */
Pali Rohár6c7ccb92022-02-15 11:23:36 +0100896 pcie_advk_wait_for_link(pcie);
Wilson Dinge51f2b12018-03-26 15:57:29 +0800897
Wilson Dinge51f2b12018-03-26 15:57:29 +0800898 return 0;
899}
900
901/**
902 * pcie_advk_probe() - Probe the PCIe bus for active link
903 *
904 * @dev: A pointer to the device being operated on
905 *
906 * Probe for an active link on the PCIe bus and configure the controller
907 * to enable this port.
908 *
909 * Return: 0 on success, else -ENODEV
910 */
911static int pcie_advk_probe(struct udevice *dev)
912{
913 struct pcie_advk *pcie = dev_get_priv(dev);
914
Pali Rohár828d3262020-08-19 15:57:07 +0200915 gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
Wilson Dinge51f2b12018-03-26 15:57:29 +0800916 GPIOD_IS_OUT);
917 /*
918 * Issue reset to add-in card through the dedicated GPIO.
919 * Some boards are connecting the card reset pin to common system
920 * reset wire and others are using separate GPIO port.
921 * In the last case we have to release a reset of the addon card
922 * using this GPIO.
923 *
924 * FIX-ME:
925 * The PCIe RESET signal is not supposed to be released along
926 * with the SOC RESET signal. It should be lowered as early as
927 * possible before PCIe PHY initialization. Moreover, the PCIe
928 * clock should be gated as well.
929 */
Pali Rohár828d3262020-08-19 15:57:07 +0200930 if (dm_gpio_is_valid(&pcie->reset_gpio)) {
Pali Rohár279b5732021-01-18 12:09:33 +0100931 dev_dbg(dev, "Toggle PCIE Reset GPIO ...\n");
Pali Rohár828d3262020-08-19 15:57:07 +0200932 dm_gpio_set_value(&pcie->reset_gpio, 1);
Pali Rohár563b85b2020-08-19 15:57:06 +0200933 mdelay(200);
Pali Rohár828d3262020-08-19 15:57:07 +0200934 dm_gpio_set_value(&pcie->reset_gpio, 0);
Pali Rohár835d9692020-08-25 10:45:04 +0200935 } else {
Pali Rohár279b5732021-01-18 12:09:33 +0100936 dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
Wilson Dinge51f2b12018-03-26 15:57:29 +0800937 }
Wilson Dinge51f2b12018-03-26 15:57:29 +0800938
Wilson Dinge51f2b12018-03-26 15:57:29 +0800939 pcie->dev = pci_get_controller(dev);
940
Pali Rohárcb056002021-09-26 00:54:42 +0200941 /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
942 pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
943 PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
944 pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
945 PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
946
Wilson Dinge51f2b12018-03-26 15:57:29 +0800947 return pcie_advk_setup_hw(pcie);
948}
949
Pali Rohár828d3262020-08-19 15:57:07 +0200950static int pcie_advk_remove(struct udevice *dev)
951{
Pali Rohár828d3262020-08-19 15:57:07 +0200952 struct pcie_advk *pcie = dev_get_priv(dev);
Pali Rohár5f50b882020-09-22 13:21:38 +0200953 u32 reg;
Pali Rohárb3217222021-05-26 17:59:40 +0200954 int i;
955
Pali Rohárcf2a5892022-02-10 14:53:43 +0100956 for (i = 0; i < ADVK_OB_WIN_COUNT; i++)
Pali Rohárb3217222021-05-26 17:59:40 +0200957 pcie_advk_disable_ob_win(pcie, i);
Pali Rohár828d3262020-08-19 15:57:07 +0200958
Pali Rohár819a43c2022-02-10 14:53:42 +0100959 reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
960 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
961 advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
Pali Rohár7b85aef2021-05-26 17:59:35 +0200962
Pali Rohárcf2a5892022-02-10 14:53:43 +0100963 reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
964 reg &= ~ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
965 advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
Pali Rohár5f50b882020-09-22 13:21:38 +0200966
Pali Rohár828d3262020-08-19 15:57:07 +0200967 return 0;
968}
969
Wilson Dinge51f2b12018-03-26 15:57:29 +0800970/**
Simon Glassd1998a92020-12-03 16:55:21 -0700971 * pcie_advk_of_to_plat() - Translate from DT to device state
Wilson Dinge51f2b12018-03-26 15:57:29 +0800972 *
973 * @dev: A pointer to the device being operated on
974 *
975 * Translate relevant data from the device tree pertaining to device @dev into
976 * state that the driver will later make use of. This state is stored in the
977 * device's private data structure.
978 *
979 * Return: 0 on success, else -EINVAL
980 */
Simon Glassd1998a92020-12-03 16:55:21 -0700981static int pcie_advk_of_to_plat(struct udevice *dev)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800982{
983 struct pcie_advk *pcie = dev_get_priv(dev);
984
985 /* Get the register base address */
Johan Jonkera12a73b2023-03-13 01:32:04 +0100986 pcie->base = dev_read_addr_ptr(dev);
987 if (!pcie->base)
Wilson Dinge51f2b12018-03-26 15:57:29 +0800988 return -EINVAL;
989
990 return 0;
991}
992
993static const struct dm_pci_ops pcie_advk_ops = {
994 .read_config = pcie_advk_read_config,
995 .write_config = pcie_advk_write_config,
996};
997
998static const struct udevice_id pcie_advk_ids[] = {
Pali Rohára544d652021-05-26 17:59:36 +0200999 { .compatible = "marvell,armada-3700-pcie" },
Wilson Dinge51f2b12018-03-26 15:57:29 +08001000 { }
1001};
1002
1003U_BOOT_DRIVER(pcie_advk) = {
1004 .name = "pcie_advk",
1005 .id = UCLASS_PCI,
1006 .of_match = pcie_advk_ids,
1007 .ops = &pcie_advk_ops,
Simon Glassd1998a92020-12-03 16:55:21 -07001008 .of_to_plat = pcie_advk_of_to_plat,
Wilson Dinge51f2b12018-03-26 15:57:29 +08001009 .probe = pcie_advk_probe,
Pali Rohár828d3262020-08-19 15:57:07 +02001010 .remove = pcie_advk_remove,
1011 .flags = DM_FLAG_OS_PREPARE,
Simon Glass41575d82020-12-03 16:55:17 -07001012 .priv_auto = sizeof(struct pcie_advk),
Wilson Dinge51f2b12018-03-26 15:57:29 +08001013};