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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a471db07fbb65a841ffc9f4f112562b945230f98 / . / board / amcc / bamboo / init.S
blob: 1459eec363845d67e8627128a2ae038cc73cebc9 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]25
26#include <ppc_asm.tmpl>
27#include <config.h>
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]28#include <asm-ppc/mmu.h>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]29
30/**************************************************************************
31 * TLB TABLE
32 *
33 * This table is used by the cpu boot code to setup the initial tlb
34 * entries. Rather than make broad assumptions in the cpu source tree,
35 * this table lets each board set things up however they like.
36 *
37 * Pointer to the table is returned in r1
38 *
39 *************************************************************************/
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]40 .section .bootpg,"ax"
41 .globl tlbtab
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]42
43tlbtab:
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]44 tlbtab_start
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]45
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]46 /*
47 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
48 * speed up boot process. It is patched after relocation to enable SA_I
49 */
50#ifndef CONFIG_NAND_SPL
51 tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
52#else
53 tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
54#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]55
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]56 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
57 tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]58
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]59 tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
Stefan Roese8a316c92005-08-01 16:49:12 +0200[diff] [blame]60
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]61 /* PCI base & peripherals */
62 tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
Stefan Roese8a316c92005-08-01 16:49:12 +0200[diff] [blame]63
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]64 tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
65 tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
Stefan Roese8a316c92005-08-01 16:49:12 +0200[diff] [blame]66
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame^]67 /* PCI */
68 tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
70 tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
71 tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
72
73 /* USB 2.0 Device */
74 tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
75
76 tlbtab_end
77
78#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
79 /*
80 * For NAND booting the first TLB has to be reconfigured to full size
81 * and with caching disabled after running from RAM!
82 */
83#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
84#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0)
85#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
86
87 .globl reconfig_tlb0
88reconfig_tlb0:
89 sync
90 isync
91 addi r4,r0,0x0000 /* TLB entry #0 */
92 lis r5,TLB00@h
93 ori r5,r5,TLB00@l
94 tlbwe r5,r4,0x0000 /* Save it out */
95 lis r5,TLB01@h
96 ori r5,r5,TLB01@l
97 tlbwe r5,r4,0x0001 /* Save it out */
98 lis r5,TLB02@h
99 ori r5,r5,TLB02@l
100 tlbwe r5,r4,0x0002 /* Save it out */
101 sync
102 isync
103 blr
104#endif