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Jerome Brunet85878392018-10-05 09:36:37 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright (C) 2018 Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * Based on code from Linux kernel:
6 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
7 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
8 */
9
10#include <common.h>
11#include <dm.h>
12#include <dm/pinctrl.h>
13#include <dt-bindings/gpio/meson-axg-gpio.h>
14
15#include "pinctrl-meson-axg.h"
16
Carlo Caione139ebe92018-12-06 08:08:11 +000017#define EE_OFF 15
Jerome Brunet85878392018-10-05 09:36:37 +020018
19/* emmc */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020020static const unsigned int emmc_nand_d0_pins[] = { PIN(BOOT_0, EE_OFF) };
21static const unsigned int emmc_nand_d1_pins[] = { PIN(BOOT_1, EE_OFF) };
22static const unsigned int emmc_nand_d2_pins[] = { PIN(BOOT_2, EE_OFF) };
23static const unsigned int emmc_nand_d3_pins[] = { PIN(BOOT_3, EE_OFF) };
24static const unsigned int emmc_nand_d4_pins[] = { PIN(BOOT_4, EE_OFF) };
25static const unsigned int emmc_nand_d5_pins[] = { PIN(BOOT_5, EE_OFF) };
26static const unsigned int emmc_nand_d6_pins[] = { PIN(BOOT_6, EE_OFF) };
27static const unsigned int emmc_nand_d7_pins[] = { PIN(BOOT_7, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020028
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020029static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
30static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
31static const unsigned int emmc_ds_pins[] = { PIN(BOOT_13, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020032
33/* nand */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020034static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
35static const unsigned int nand_ale_pins[] = { PIN(BOOT_9, EE_OFF) };
36static const unsigned int nand_cle_pins[] = { PIN(BOOT_10, EE_OFF) };
37static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_11, EE_OFF) };
38static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_12, EE_OFF) };
39static const unsigned int nand_rb0_pins[] = { PIN(BOOT_13, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020040
41/* nor */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020042static const unsigned int nor_hold_pins[] = { PIN(BOOT_3, EE_OFF) };
43static const unsigned int nor_d_pins[] = { PIN(BOOT_4, EE_OFF) };
44static const unsigned int nor_q_pins[] = { PIN(BOOT_5, EE_OFF) };
45static const unsigned int nor_c_pins[] = { PIN(BOOT_6, EE_OFF) };
46static const unsigned int nor_wp_pins[] = { PIN(BOOT_9, EE_OFF) };
47static const unsigned int nor_cs_pins[] = { PIN(BOOT_14, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020048
49/* sdio */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020050static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
51static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
52static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
53static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
54static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_4, EE_OFF) };
55static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_5, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020056
57/* spi0 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020058static const unsigned int spi0_clk_pins[] = { PIN(GPIOZ_0, EE_OFF) };
59static const unsigned int spi0_mosi_pins[] = { PIN(GPIOZ_1, EE_OFF) };
60static const unsigned int spi0_miso_pins[] = { PIN(GPIOZ_2, EE_OFF) };
61static const unsigned int spi0_ss0_pins[] = { PIN(GPIOZ_3, EE_OFF) };
62static const unsigned int spi0_ss1_pins[] = { PIN(GPIOZ_4, EE_OFF) };
63static const unsigned int spi0_ss2_pins[] = { PIN(GPIOZ_5, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020064
65/* spi1 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020066static const unsigned int spi1_clk_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
67static const unsigned int spi1_mosi_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
68static const unsigned int spi1_miso_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
69static const unsigned int spi1_ss0_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020070
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020071static const unsigned int spi1_clk_a_pins[] = { PIN(GPIOA_4, EE_OFF) };
72static const unsigned int spi1_mosi_a_pins[] = { PIN(GPIOA_2, EE_OFF) };
73static const unsigned int spi1_miso_a_pins[] = { PIN(GPIOA_3, EE_OFF) };
74static const unsigned int spi1_ss0_a_pins[] = { PIN(GPIOA_5, EE_OFF) };
75static const unsigned int spi1_ss1_pins[] = { PIN(GPIOA_6, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020076
77/* i2c0 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020078static const unsigned int i2c0_sck_pins[] = { PIN(GPIOZ_6, EE_OFF) };
79static const unsigned int i2c0_sda_pins[] = { PIN(GPIOZ_7, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020080
81/* i2c1 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020082static const unsigned int i2c1_sck_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
83static const unsigned int i2c1_sda_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020084
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020085static const unsigned int i2c1_sck_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
86static const unsigned int i2c1_sda_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020087
88/* i2c2 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020089static const unsigned int i2c2_sck_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
90static const unsigned int i2c2_sda_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020091
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020092static const unsigned int i2c2_sda_a_pins[] = { PIN(GPIOA_17, EE_OFF) };
93static const unsigned int i2c2_sck_a_pins[] = { PIN(GPIOA_18, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020094
95/* i2c3 */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020096static const unsigned int i2c3_sda_a6_pins[] = { PIN(GPIOA_6, EE_OFF) };
97static const unsigned int i2c3_sck_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +020098
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +020099static const unsigned int i2c3_sda_a12_pins[] = { PIN(GPIOA_12, EE_OFF) };
100static const unsigned int i2c3_sck_a13_pins[] = { PIN(GPIOA_13, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200101
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200102static const unsigned int i2c3_sda_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
103static const unsigned int i2c3_sck_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200104
105/* uart_a */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200106static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_11, EE_OFF) };
107static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_10, EE_OFF) };
108static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_8, EE_OFF) };
109static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_9, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200110
111/* uart_b */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200112static const unsigned int uart_rts_b_z_pins[] = { PIN(GPIOZ_0, EE_OFF) };
113static const unsigned int uart_cts_b_z_pins[] = { PIN(GPIOZ_1, EE_OFF) };
114static const unsigned int uart_tx_b_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
115static const unsigned int uart_rx_b_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200116
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200117static const unsigned int uart_rts_b_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
118static const unsigned int uart_cts_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
119static const unsigned int uart_tx_b_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
120static const unsigned int uart_rx_b_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200121
122/* uart_ao_b */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200123static const unsigned int uart_ao_tx_b_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
124static const unsigned int uart_ao_rx_b_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
125static const unsigned int uart_ao_cts_b_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
126static const unsigned int uart_ao_rts_b_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200127
128/* pwm_a */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200129static const unsigned int pwm_a_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200130
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200131static const unsigned int pwm_a_x18_pins[] = { PIN(GPIOX_18, EE_OFF) };
132static const unsigned int pwm_a_x20_pins[] = { PIN(GPIOX_20, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200133
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200134static const unsigned int pwm_a_a_pins[] = { PIN(GPIOA_14, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200135
136/* pwm_b */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200137static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200138
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200139static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200140
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200141static const unsigned int pwm_b_a_pins[] = { PIN(GPIOA_15, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200142
143/* pwm_c */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200144static const unsigned int pwm_c_x10_pins[] = { PIN(GPIOX_10, EE_OFF) };
145static const unsigned int pwm_c_x17_pins[] = { PIN(GPIOX_17, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200146
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200147static const unsigned int pwm_c_a_pins[] = { PIN(GPIOA_16, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200148
149/* pwm_d */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200150static const unsigned int pwm_d_x11_pins[] = { PIN(GPIOX_11, EE_OFF) };
151static const unsigned int pwm_d_x16_pins[] = { PIN(GPIOX_16, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200152
153/* pwm_vs */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200154static const unsigned int pwm_vs_pins[] = { PIN(GPIOA_0, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200155
156/* spdif_in */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200157static const unsigned int spdif_in_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200158
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200159static const unsigned int spdif_in_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
160static const unsigned int spdif_in_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
161static const unsigned int spdif_in_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
162static const unsigned int spdif_in_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200163
164/* spdif_out */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200165static const unsigned int spdif_out_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200166
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200167static const unsigned int spdif_out_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
168static const unsigned int spdif_out_a11_pins[] = { PIN(GPIOA_11, EE_OFF) };
169static const unsigned int spdif_out_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
170static const unsigned int spdif_out_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200171
172/* jtag_ee */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200173static const unsigned int jtag_tdo_x_pins[] = { PIN(GPIOX_0, EE_OFF) };
174static const unsigned int jtag_tdi_x_pins[] = { PIN(GPIOX_1, EE_OFF) };
175static const unsigned int jtag_clk_x_pins[] = { PIN(GPIOX_4, EE_OFF) };
176static const unsigned int jtag_tms_x_pins[] = { PIN(GPIOX_5, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200177
178/* eth */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200179static const unsigned int eth_txd0_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
180static const unsigned int eth_txd1_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
181static const unsigned int eth_txen_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
182static const unsigned int eth_rgmii_rx_clk_x_pins[] = { PIN(GPIOX_12, EE_OFF) };
183static const unsigned int eth_rxd0_x_pins[] = { PIN(GPIOX_13, EE_OFF) };
184static const unsigned int eth_rxd1_x_pins[] = { PIN(GPIOX_14, EE_OFF) };
185static const unsigned int eth_rx_dv_x_pins[] = { PIN(GPIOX_15, EE_OFF) };
186static const unsigned int eth_mdio_x_pins[] = { PIN(GPIOX_21, EE_OFF) };
187static const unsigned int eth_mdc_x_pins[] = { PIN(GPIOX_22, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200188
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200189static const unsigned int eth_txd0_y_pins[] = { PIN(GPIOY_10, EE_OFF) };
190static const unsigned int eth_txd1_y_pins[] = { PIN(GPIOY_11, EE_OFF) };
191static const unsigned int eth_txen_y_pins[] = { PIN(GPIOY_9, EE_OFF) };
192static const unsigned int eth_rgmii_rx_clk_y_pins[] = { PIN(GPIOY_2, EE_OFF) };
193static const unsigned int eth_rxd0_y_pins[] = { PIN(GPIOY_4, EE_OFF) };
194static const unsigned int eth_rxd1_y_pins[] = { PIN(GPIOY_5, EE_OFF) };
195static const unsigned int eth_rx_dv_y_pins[] = { PIN(GPIOY_3, EE_OFF) };
196static const unsigned int eth_mdio_y_pins[] = { PIN(GPIOY_0, EE_OFF) };
197static const unsigned int eth_mdc_y_pins[] = { PIN(GPIOY_1, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200198
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200199static const unsigned int eth_rxd2_rgmii_pins[] = { PIN(GPIOY_6, EE_OFF) };
200static const unsigned int eth_rxd3_rgmii_pins[] = { PIN(GPIOY_7, EE_OFF) };
201static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOY_8, EE_OFF) };
202static const unsigned int eth_txd2_rgmii_pins[] = { PIN(GPIOY_12, EE_OFF) };
203static const unsigned int eth_txd3_rgmii_pins[] = { PIN(GPIOY_13, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200204
205/* pdm */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200206static const unsigned int pdm_dclk_a14_pins[] = { PIN(GPIOA_14, EE_OFF) };
207static const unsigned int pdm_dclk_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
208static const unsigned int pdm_din0_pins[] = { PIN(GPIOA_15, EE_OFF) };
209static const unsigned int pdm_din1_pins[] = { PIN(GPIOA_16, EE_OFF) };
210static const unsigned int pdm_din2_pins[] = { PIN(GPIOA_17, EE_OFF) };
211static const unsigned int pdm_din3_pins[] = { PIN(GPIOA_18, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200212
213/* mclk */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200214static const unsigned int mclk_c_pins[] = { PIN(GPIOA_0, EE_OFF) };
215static const unsigned int mclk_b_pins[] = { PIN(GPIOA_1, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200216
217/* tdm */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200218static const unsigned int tdma_sclk_pins[] = { PIN(GPIOX_12, EE_OFF) };
219static const unsigned int tdma_sclk_slv_pins[] = { PIN(GPIOX_12, EE_OFF) };
220static const unsigned int tdma_fs_pins[] = { PIN(GPIOX_13, EE_OFF) };
221static const unsigned int tdma_fs_slv_pins[] = { PIN(GPIOX_13, EE_OFF) };
222static const unsigned int tdma_din0_pins[] = { PIN(GPIOX_14, EE_OFF) };
223static const unsigned int tdma_dout0_x14_pins[] = { PIN(GPIOX_14, EE_OFF) };
224static const unsigned int tdma_dout0_x15_pins[] = { PIN(GPIOX_15, EE_OFF) };
225static const unsigned int tdma_dout1_pins[] = { PIN(GPIOX_15, EE_OFF) };
226static const unsigned int tdma_din1_pins[] = { PIN(GPIOX_15, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200227
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200228static const unsigned int tdmc_sclk_pins[] = { PIN(GPIOA_2, EE_OFF) };
229static const unsigned int tdmc_sclk_slv_pins[] = { PIN(GPIOA_2, EE_OFF) };
230static const unsigned int tdmc_fs_pins[] = { PIN(GPIOA_3, EE_OFF) };
231static const unsigned int tdmc_fs_slv_pins[] = { PIN(GPIOA_3, EE_OFF) };
232static const unsigned int tdmc_din0_pins[] = { PIN(GPIOA_4, EE_OFF) };
233static const unsigned int tdmc_dout0_pins[] = { PIN(GPIOA_4, EE_OFF) };
234static const unsigned int tdmc_din1_pins[] = { PIN(GPIOA_5, EE_OFF) };
235static const unsigned int tdmc_dout1_pins[] = { PIN(GPIOA_5, EE_OFF) };
236static const unsigned int tdmc_din2_pins[] = { PIN(GPIOA_6, EE_OFF) };
237static const unsigned int tdmc_dout2_pins[] = { PIN(GPIOA_6, EE_OFF) };
238static const unsigned int tdmc_din3_pins[] = { PIN(GPIOA_7, EE_OFF) };
239static const unsigned int tdmc_dout3_pins[] = { PIN(GPIOA_7, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200240
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200241static const unsigned int tdmb_sclk_pins[] = { PIN(GPIOA_8, EE_OFF) };
242static const unsigned int tdmb_sclk_slv_pins[] = { PIN(GPIOA_8, EE_OFF) };
243static const unsigned int tdmb_fs_pins[] = { PIN(GPIOA_9, EE_OFF) };
244static const unsigned int tdmb_fs_slv_pins[] = { PIN(GPIOA_9, EE_OFF) };
245static const unsigned int tdmb_din0_pins[] = { PIN(GPIOA_10, EE_OFF) };
246static const unsigned int tdmb_dout0_pins[] = { PIN(GPIOA_10, EE_OFF) };
247static const unsigned int tdmb_din1_pins[] = { PIN(GPIOA_11, EE_OFF) };
248static const unsigned int tdmb_dout1_pins[] = { PIN(GPIOA_11, EE_OFF) };
249static const unsigned int tdmb_din2_pins[] = { PIN(GPIOA_12, EE_OFF) };
250static const unsigned int tdmb_dout2_pins[] = { PIN(GPIOA_12, EE_OFF) };
251static const unsigned int tdmb_din3_pins[] = { PIN(GPIOA_13, EE_OFF) };
252static const unsigned int tdmb_dout3_pins[] = { PIN(GPIOA_13, EE_OFF) };
Jerome Brunet85878392018-10-05 09:36:37 +0200253
254static struct meson_pmx_group meson_axg_periphs_groups[] = {
255 GPIO_GROUP(GPIOZ_0, EE_OFF),
256 GPIO_GROUP(GPIOZ_1, EE_OFF),
257 GPIO_GROUP(GPIOZ_2, EE_OFF),
258 GPIO_GROUP(GPIOZ_3, EE_OFF),
259 GPIO_GROUP(GPIOZ_4, EE_OFF),
260 GPIO_GROUP(GPIOZ_5, EE_OFF),
261 GPIO_GROUP(GPIOZ_6, EE_OFF),
262 GPIO_GROUP(GPIOZ_7, EE_OFF),
263 GPIO_GROUP(GPIOZ_8, EE_OFF),
264 GPIO_GROUP(GPIOZ_9, EE_OFF),
265 GPIO_GROUP(GPIOZ_10, EE_OFF),
266
267 GPIO_GROUP(BOOT_0, EE_OFF),
268 GPIO_GROUP(BOOT_1, EE_OFF),
269 GPIO_GROUP(BOOT_2, EE_OFF),
270 GPIO_GROUP(BOOT_3, EE_OFF),
271 GPIO_GROUP(BOOT_4, EE_OFF),
272 GPIO_GROUP(BOOT_5, EE_OFF),
273 GPIO_GROUP(BOOT_6, EE_OFF),
274 GPIO_GROUP(BOOT_7, EE_OFF),
275 GPIO_GROUP(BOOT_8, EE_OFF),
276 GPIO_GROUP(BOOT_9, EE_OFF),
277 GPIO_GROUP(BOOT_10, EE_OFF),
278 GPIO_GROUP(BOOT_11, EE_OFF),
279 GPIO_GROUP(BOOT_12, EE_OFF),
280 GPIO_GROUP(BOOT_13, EE_OFF),
281 GPIO_GROUP(BOOT_14, EE_OFF),
282
283 GPIO_GROUP(GPIOA_0, EE_OFF),
284 GPIO_GROUP(GPIOA_1, EE_OFF),
285 GPIO_GROUP(GPIOA_2, EE_OFF),
286 GPIO_GROUP(GPIOA_3, EE_OFF),
287 GPIO_GROUP(GPIOA_4, EE_OFF),
288 GPIO_GROUP(GPIOA_5, EE_OFF),
289 GPIO_GROUP(GPIOA_6, EE_OFF),
290 GPIO_GROUP(GPIOA_7, EE_OFF),
291 GPIO_GROUP(GPIOA_8, EE_OFF),
292 GPIO_GROUP(GPIOA_9, EE_OFF),
293 GPIO_GROUP(GPIOA_10, EE_OFF),
294 GPIO_GROUP(GPIOA_11, EE_OFF),
295 GPIO_GROUP(GPIOA_12, EE_OFF),
296 GPIO_GROUP(GPIOA_13, EE_OFF),
297 GPIO_GROUP(GPIOA_14, EE_OFF),
298 GPIO_GROUP(GPIOA_15, EE_OFF),
299 GPIO_GROUP(GPIOA_16, EE_OFF),
300 GPIO_GROUP(GPIOA_17, EE_OFF),
Neil Armstrong38c1c6f2020-10-02 09:32:12 +0200301 GPIO_GROUP(GPIOA_18, EE_OFF),
Jerome Brunet85878392018-10-05 09:36:37 +0200302 GPIO_GROUP(GPIOA_19, EE_OFF),
303 GPIO_GROUP(GPIOA_20, EE_OFF),
304
305 GPIO_GROUP(GPIOX_0, EE_OFF),
306 GPIO_GROUP(GPIOX_1, EE_OFF),
307 GPIO_GROUP(GPIOX_2, EE_OFF),
308 GPIO_GROUP(GPIOX_3, EE_OFF),
309 GPIO_GROUP(GPIOX_4, EE_OFF),
310 GPIO_GROUP(GPIOX_5, EE_OFF),
311 GPIO_GROUP(GPIOX_6, EE_OFF),
312 GPIO_GROUP(GPIOX_7, EE_OFF),
313 GPIO_GROUP(GPIOX_8, EE_OFF),
314 GPIO_GROUP(GPIOX_9, EE_OFF),
315 GPIO_GROUP(GPIOX_10, EE_OFF),
316 GPIO_GROUP(GPIOX_11, EE_OFF),
317 GPIO_GROUP(GPIOX_12, EE_OFF),
318 GPIO_GROUP(GPIOX_13, EE_OFF),
319 GPIO_GROUP(GPIOX_14, EE_OFF),
320 GPIO_GROUP(GPIOX_15, EE_OFF),
321 GPIO_GROUP(GPIOX_16, EE_OFF),
322 GPIO_GROUP(GPIOX_17, EE_OFF),
323 GPIO_GROUP(GPIOX_18, EE_OFF),
324 GPIO_GROUP(GPIOX_19, EE_OFF),
325 GPIO_GROUP(GPIOX_20, EE_OFF),
326 GPIO_GROUP(GPIOX_21, EE_OFF),
327 GPIO_GROUP(GPIOX_22, EE_OFF),
328
329 GPIO_GROUP(GPIOY_0, EE_OFF),
330 GPIO_GROUP(GPIOY_1, EE_OFF),
331 GPIO_GROUP(GPIOY_2, EE_OFF),
332 GPIO_GROUP(GPIOY_3, EE_OFF),
333 GPIO_GROUP(GPIOY_4, EE_OFF),
334 GPIO_GROUP(GPIOY_5, EE_OFF),
335 GPIO_GROUP(GPIOY_6, EE_OFF),
336 GPIO_GROUP(GPIOY_7, EE_OFF),
337 GPIO_GROUP(GPIOY_8, EE_OFF),
338 GPIO_GROUP(GPIOY_9, EE_OFF),
339 GPIO_GROUP(GPIOY_10, EE_OFF),
340 GPIO_GROUP(GPIOY_11, EE_OFF),
341 GPIO_GROUP(GPIOY_12, EE_OFF),
342 GPIO_GROUP(GPIOY_13, EE_OFF),
343 GPIO_GROUP(GPIOY_14, EE_OFF),
344 GPIO_GROUP(GPIOY_15, EE_OFF),
345
346 /* bank BOOT */
347 GROUP(emmc_nand_d0, 1),
348 GROUP(emmc_nand_d1, 1),
349 GROUP(emmc_nand_d2, 1),
350 GROUP(emmc_nand_d3, 1),
351 GROUP(emmc_nand_d4, 1),
352 GROUP(emmc_nand_d5, 1),
353 GROUP(emmc_nand_d6, 1),
354 GROUP(emmc_nand_d7, 1),
355 GROUP(emmc_clk, 1),
356 GROUP(emmc_cmd, 1),
357 GROUP(emmc_ds, 1),
358 GROUP(nand_ce0, 2),
359 GROUP(nand_ale, 2),
360 GROUP(nand_cle, 2),
361 GROUP(nand_wen_clk, 2),
362 GROUP(nand_ren_wr, 2),
363 GROUP(nand_rb0, 2),
364 GROUP(nor_hold, 3),
365 GROUP(nor_d, 3),
366 GROUP(nor_q, 3),
367 GROUP(nor_c, 3),
368 GROUP(nor_wp, 3),
369 GROUP(nor_cs, 3),
370
371 /* bank GPIOZ */
372 GROUP(spi0_clk, 1),
373 GROUP(spi0_mosi, 1),
374 GROUP(spi0_miso, 1),
375 GROUP(spi0_ss0, 1),
376 GROUP(spi0_ss1, 1),
377 GROUP(spi0_ss2, 1),
378 GROUP(i2c0_sck, 1),
379 GROUP(i2c0_sda, 1),
380 GROUP(i2c1_sck_z, 1),
381 GROUP(i2c1_sda_z, 1),
382 GROUP(uart_rts_b_z, 2),
383 GROUP(uart_cts_b_z, 2),
384 GROUP(uart_tx_b_z, 2),
385 GROUP(uart_rx_b_z, 2),
386 GROUP(pwm_a_z, 2),
387 GROUP(pwm_b_z, 2),
388 GROUP(spdif_in_z, 3),
389 GROUP(spdif_out_z, 3),
390 GROUP(uart_ao_tx_b_z, 2),
391 GROUP(uart_ao_rx_b_z, 2),
392 GROUP(uart_ao_cts_b_z, 2),
393 GROUP(uart_ao_rts_b_z, 2),
394
395 /* bank GPIOX */
396 GROUP(sdio_d0, 1),
397 GROUP(sdio_d1, 1),
398 GROUP(sdio_d2, 1),
399 GROUP(sdio_d3, 1),
400 GROUP(sdio_clk, 1),
401 GROUP(sdio_cmd, 1),
402 GROUP(i2c1_sck_x, 1),
403 GROUP(i2c1_sda_x, 1),
404 GROUP(i2c2_sck_x, 1),
405 GROUP(i2c2_sda_x, 1),
406 GROUP(uart_rts_a, 1),
407 GROUP(uart_cts_a, 1),
408 GROUP(uart_tx_a, 1),
409 GROUP(uart_rx_a, 1),
410 GROUP(uart_rts_b_x, 2),
411 GROUP(uart_cts_b_x, 2),
412 GROUP(uart_tx_b_x, 2),
413 GROUP(uart_rx_b_x, 2),
414 GROUP(jtag_tdo_x, 2),
415 GROUP(jtag_tdi_x, 2),
416 GROUP(jtag_clk_x, 2),
417 GROUP(jtag_tms_x, 2),
418 GROUP(spi1_clk_x, 4),
419 GROUP(spi1_mosi_x, 4),
420 GROUP(spi1_miso_x, 4),
421 GROUP(spi1_ss0_x, 4),
422 GROUP(pwm_a_x18, 3),
423 GROUP(pwm_a_x20, 1),
424 GROUP(pwm_b_x, 3),
425 GROUP(pwm_c_x10, 3),
426 GROUP(pwm_c_x17, 3),
427 GROUP(pwm_d_x11, 3),
428 GROUP(pwm_d_x16, 3),
429 GROUP(eth_txd0_x, 4),
430 GROUP(eth_txd1_x, 4),
431 GROUP(eth_txen_x, 4),
432 GROUP(eth_rgmii_rx_clk_x, 4),
433 GROUP(eth_rxd0_x, 4),
434 GROUP(eth_rxd1_x, 4),
435 GROUP(eth_rx_dv_x, 4),
436 GROUP(eth_mdio_x, 4),
437 GROUP(eth_mdc_x, 4),
438 GROUP(tdma_sclk, 1),
439 GROUP(tdma_sclk_slv, 2),
440 GROUP(tdma_fs, 1),
441 GROUP(tdma_fs_slv, 2),
442 GROUP(tdma_din0, 1),
443 GROUP(tdma_dout0_x14, 2),
444 GROUP(tdma_dout0_x15, 1),
445 GROUP(tdma_dout1, 2),
446 GROUP(tdma_din1, 3),
447
448 /* bank GPIOY */
449 GROUP(eth_txd0_y, 1),
450 GROUP(eth_txd1_y, 1),
451 GROUP(eth_txen_y, 1),
452 GROUP(eth_rgmii_rx_clk_y, 1),
453 GROUP(eth_rxd0_y, 1),
454 GROUP(eth_rxd1_y, 1),
455 GROUP(eth_rx_dv_y, 1),
456 GROUP(eth_mdio_y, 1),
457 GROUP(eth_mdc_y, 1),
458 GROUP(eth_rxd2_rgmii, 1),
459 GROUP(eth_rxd3_rgmii, 1),
460 GROUP(eth_rgmii_tx_clk, 1),
461 GROUP(eth_txd2_rgmii, 1),
462 GROUP(eth_txd3_rgmii, 1),
463
464 /* bank GPIOA */
465 GROUP(spdif_out_a1, 4),
466 GROUP(spdif_out_a11, 3),
467 GROUP(spdif_out_a19, 2),
468 GROUP(spdif_out_a20, 1),
469 GROUP(spdif_in_a1, 3),
470 GROUP(spdif_in_a7, 3),
471 GROUP(spdif_in_a19, 1),
472 GROUP(spdif_in_a20, 2),
473 GROUP(spi1_clk_a, 3),
474 GROUP(spi1_mosi_a, 3),
475 GROUP(spi1_miso_a, 3),
476 GROUP(spi1_ss0_a, 3),
477 GROUP(spi1_ss1, 3),
478 GROUP(pwm_a_a, 3),
479 GROUP(pwm_b_a, 3),
480 GROUP(pwm_c_a, 3),
481 GROUP(pwm_vs, 2),
482 GROUP(i2c2_sda_a, 3),
483 GROUP(i2c2_sck_a, 3),
484 GROUP(i2c3_sda_a6, 4),
485 GROUP(i2c3_sck_a7, 4),
486 GROUP(i2c3_sda_a12, 4),
487 GROUP(i2c3_sck_a13, 4),
488 GROUP(i2c3_sda_a19, 4),
489 GROUP(i2c3_sck_a20, 4),
490 GROUP(pdm_dclk_a14, 1),
491 GROUP(pdm_dclk_a19, 3),
492 GROUP(pdm_din0, 1),
493 GROUP(pdm_din1, 1),
494 GROUP(pdm_din2, 1),
495 GROUP(pdm_din3, 1),
496 GROUP(mclk_c, 1),
497 GROUP(mclk_b, 1),
498 GROUP(tdmc_sclk, 1),
499 GROUP(tdmc_sclk_slv, 2),
500 GROUP(tdmc_fs, 1),
501 GROUP(tdmc_fs_slv, 2),
502 GROUP(tdmc_din0, 2),
503 GROUP(tdmc_dout0, 1),
504 GROUP(tdmc_din1, 2),
505 GROUP(tdmc_dout1, 1),
506 GROUP(tdmc_din2, 2),
507 GROUP(tdmc_dout2, 1),
508 GROUP(tdmc_din3, 2),
509 GROUP(tdmc_dout3, 1),
510 GROUP(tdmb_sclk, 1),
511 GROUP(tdmb_sclk_slv, 2),
512 GROUP(tdmb_fs, 1),
513 GROUP(tdmb_fs_slv, 2),
514 GROUP(tdmb_din0, 2),
515 GROUP(tdmb_dout0, 1),
516 GROUP(tdmb_din1, 2),
517 GROUP(tdmb_dout1, 1),
518 GROUP(tdmb_din2, 2),
519 GROUP(tdmb_dout2, 1),
520 GROUP(tdmb_din3, 2),
521 GROUP(tdmb_dout3, 1),
522};
523
524/* uart_ao_a */
525static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
526static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
527static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
528static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
529
530/* uart_ao_b */
531static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
532static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
533static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
534static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
535
536/* i2c_ao */
537static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
538static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
539static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
540static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
541static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
542static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
543
544/* i2c_ao_slave */
545static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
546static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
547
548/* ir_in */
549static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
550
551/* ir_out */
552static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
553
554/* pwm_ao_a */
555static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
556
557/* pwm_ao_b */
558static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
559static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
560
561/* pwm_ao_c */
562static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
563static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
564
565/* pwm_ao_d */
566static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
567
568/* jtag_ao */
569static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
570static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
571static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
572static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
573
574static struct meson_pmx_group meson_axg_aobus_groups[] = {
575 GPIO_GROUP(GPIOAO_0, 0),
576 GPIO_GROUP(GPIOAO_1, 0),
577 GPIO_GROUP(GPIOAO_2, 0),
578 GPIO_GROUP(GPIOAO_3, 0),
579 GPIO_GROUP(GPIOAO_4, 0),
580 GPIO_GROUP(GPIOAO_5, 0),
581 GPIO_GROUP(GPIOAO_6, 0),
582 GPIO_GROUP(GPIOAO_7, 0),
583 GPIO_GROUP(GPIOAO_8, 0),
584 GPIO_GROUP(GPIOAO_9, 0),
585 GPIO_GROUP(GPIOAO_10, 0),
586 GPIO_GROUP(GPIOAO_11, 0),
587 GPIO_GROUP(GPIOAO_12, 0),
588 GPIO_GROUP(GPIOAO_13, 0),
589 GPIO_GROUP(GPIO_TEST_N, 0),
590
591 /* bank AO */
592 GROUP(uart_ao_tx_a, 1),
593 GROUP(uart_ao_rx_a, 1),
594 GROUP(uart_ao_cts_a, 2),
595 GROUP(uart_ao_rts_a, 2),
596 GROUP(uart_ao_tx_b, 1),
597 GROUP(uart_ao_rx_b, 1),
598 GROUP(uart_ao_cts_b, 1),
599 GROUP(uart_ao_rts_b, 1),
600 GROUP(i2c_ao_sck_4, 2),
601 GROUP(i2c_ao_sda_5, 2),
602 GROUP(i2c_ao_sck_8, 2),
603 GROUP(i2c_ao_sda_9, 2),
604 GROUP(i2c_ao_sck_10, 2),
605 GROUP(i2c_ao_sda_11, 2),
606 GROUP(i2c_ao_slave_sck, 1),
607 GROUP(i2c_ao_slave_sda, 1),
608 GROUP(remote_input_ao, 1),
609 GROUP(remote_out_ao, 1),
610 GROUP(pwm_ao_a, 3),
611 GROUP(pwm_ao_b_ao2, 3),
612 GROUP(pwm_ao_b_ao12, 3),
613 GROUP(pwm_ao_c_ao8, 3),
614 GROUP(pwm_ao_c_ao13, 3),
615 GROUP(pwm_ao_d, 3),
616 GROUP(jtag_ao_tdi, 4),
617 GROUP(jtag_ao_tdo, 4),
618 GROUP(jtag_ao_clk, 4),
619 GROUP(jtag_ao_tms, 4),
620};
621
622static const char * const gpio_periphs_groups[] = {
623 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
624 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
625 "GPIOZ_10",
626
627 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
628 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
629 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
630
631 "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
632 "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
633 "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
634 "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
635 "GPIOA_20",
636
637 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
638 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
639 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
640 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
641 "GPIOX_20", "GPIOX_21", "GPIOX_22",
642
643 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
644 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
645 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
646 "GPIOY_15",
647};
648
649static const char * const emmc_groups[] = {
650 "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
651 "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
652 "emmc_nand_d6", "emmc_nand_d7",
653 "emmc_clk", "emmc_cmd", "emmc_ds",
654};
655
656static const char * const nand_groups[] = {
657 "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
658 "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
659 "emmc_nand_d6", "emmc_nand_d7",
660 "nand_ce0", "nand_ale", "nand_cle",
661 "nand_wen_clk", "nand_ren_wr", "nand_rb0",
662};
663
664static const char * const nor_groups[] = {
665 "nor_d", "nor_q", "nor_c", "nor_cs",
666 "nor_hold", "nor_wp",
667};
668
669static const char * const sdio_groups[] = {
670 "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
671 "sdio_cmd", "sdio_clk",
672};
673
674static const char * const spi0_groups[] = {
675 "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
676 "spi0_ss1", "spi0_ss2"
677};
678
679static const char * const spi1_groups[] = {
680 "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
681 "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
682 "spi1_ss1"
683};
684
685static const char * const uart_a_groups[] = {
686 "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
687};
688
689static const char * const uart_b_groups[] = {
690 "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
691 "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
692};
693
694static const char * const uart_ao_b_z_groups[] = {
695 "uart_ao_tx_b_z", "uart_ao_rx_b_z",
696 "uart_ao_cts_b_z", "uart_ao_rts_b_z",
697};
698
699static const char * const i2c0_groups[] = {
700 "i2c0_sck", "i2c0_sda",
701};
702
703static const char * const i2c1_groups[] = {
704 "i2c1_sck_z", "i2c1_sda_z",
705 "i2c1_sck_x", "i2c1_sda_x",
706};
707
708static const char * const i2c2_groups[] = {
709 "i2c2_sck_x", "i2c2_sda_x",
710 "i2c2_sda_a", "i2c2_sck_a",
711};
712
713static const char * const i2c3_groups[] = {
714 "i2c3_sda_a6", "i2c3_sck_a7",
715 "i2c3_sda_a12", "i2c3_sck_a13",
716 "i2c3_sda_a19", "i2c3_sck_a20",
717};
718
719static const char * const eth_groups[] = {
720 "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
721 "eth_txd2_rgmii", "eth_txd3_rgmii",
722 "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
723 "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
724 "eth_mdc_x",
725 "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
726 "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
727 "eth_mdc_y",
728};
729
730static const char * const pwm_a_groups[] = {
731 "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
732};
733
734static const char * const pwm_b_groups[] = {
735 "pwm_b_z", "pwm_b_x", "pwm_b_a",
736};
737
738static const char * const pwm_c_groups[] = {
739 "pwm_c_x10", "pwm_c_x17", "pwm_c_a",
740};
741
742static const char * const pwm_d_groups[] = {
743 "pwm_d_x11", "pwm_d_x16",
744};
745
746static const char * const pwm_vs_groups[] = {
747 "pwm_vs",
748};
749
750static const char * const spdif_out_groups[] = {
751 "spdif_out_z", "spdif_out_a1", "spdif_out_a11",
752 "spdif_out_a19", "spdif_out_a20",
753};
754
755static const char * const spdif_in_groups[] = {
756 "spdif_in_z", "spdif_in_a1", "spdif_in_a7",
757 "spdif_in_a19", "spdif_in_a20",
758};
759
760static const char * const jtag_ee_groups[] = {
761 "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
762 "jtag_tms_x",
763};
764
765static const char * const pdm_groups[] = {
766 "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
767 "pdm_dclk_a14", "pdm_dclk_a19",
768};
769
770static const char * const gpio_aobus_groups[] = {
771 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
772 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
773 "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
774 "GPIO_TEST_N",
775};
776
777static const char * const uart_ao_a_groups[] = {
778 "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
779};
780
781static const char * const uart_ao_b_groups[] = {
782 "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
783};
784
785static const char * const i2c_ao_groups[] = {
786 "i2c_ao_sck_4", "i2c_ao_sda_5",
787 "i2c_ao_sck_8", "i2c_ao_sda_9",
788 "i2c_ao_sck_10", "i2c_ao_sda_11",
789};
790
791static const char * const i2c_ao_slave_groups[] = {
792 "i2c_ao_slave_sck", "i2c_ao_slave_sda",
793};
794
795static const char * const remote_input_ao_groups[] = {
796 "remote_input_ao",
797};
798
799static const char * const remote_out_ao_groups[] = {
800 "remote_out_ao",
801};
802
803static const char * const pwm_ao_a_groups[] = {
804 "pwm_ao_a",
805};
806
807static const char * const pwm_ao_b_groups[] = {
808 "pwm_ao_b_ao2", "pwm_ao_b_ao12",
809};
810
811static const char * const pwm_ao_c_groups[] = {
812 "pwm_ao_c_ao8", "pwm_ao_c_ao13",
813};
814
815static const char * const pwm_ao_d_groups[] = {
816 "pwm_ao_d",
817};
818
819static const char * const jtag_ao_groups[] = {
820 "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
821};
822
823static const char * const mclk_c_groups[] = {
824 "mclk_c",
825};
826
827static const char * const mclk_b_groups[] = {
828 "mclk_b",
829};
830
831static const char * const tdma_groups[] = {
832 "tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
833 "tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
834 "tdma_din1",
835};
836
837static const char * const tdmc_groups[] = {
838 "tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
839 "tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1",
840 "tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3",
841};
842
843static const char * const tdmb_groups[] = {
844 "tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
845 "tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1",
846 "tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3",
847};
848
849static struct meson_pmx_func meson_axg_periphs_functions[] = {
850 FUNCTION(gpio_periphs),
851 FUNCTION(emmc),
852 FUNCTION(nor),
853 FUNCTION(spi0),
854 FUNCTION(spi1),
855 FUNCTION(sdio),
856 FUNCTION(nand),
857 FUNCTION(uart_a),
858 FUNCTION(uart_b),
859 FUNCTION(uart_ao_b_z),
860 FUNCTION(i2c0),
861 FUNCTION(i2c1),
862 FUNCTION(i2c2),
863 FUNCTION(i2c3),
864 FUNCTION(eth),
865 FUNCTION(pwm_a),
866 FUNCTION(pwm_b),
867 FUNCTION(pwm_c),
868 FUNCTION(pwm_d),
869 FUNCTION(pwm_vs),
870 FUNCTION(spdif_out),
871 FUNCTION(spdif_in),
872 FUNCTION(jtag_ee),
873 FUNCTION(pdm),
874 FUNCTION(mclk_b),
875 FUNCTION(mclk_c),
876 FUNCTION(tdma),
877 FUNCTION(tdmb),
878 FUNCTION(tdmc),
879};
880
881static struct meson_pmx_func meson_axg_aobus_functions[] = {
882 FUNCTION(gpio_aobus),
883 FUNCTION(uart_ao_a),
884 FUNCTION(uart_ao_b),
885 FUNCTION(i2c_ao),
886 FUNCTION(i2c_ao_slave),
887 FUNCTION(remote_input_ao),
888 FUNCTION(remote_out_ao),
889 FUNCTION(pwm_ao_a),
890 FUNCTION(pwm_ao_b),
891 FUNCTION(pwm_ao_c),
892 FUNCTION(pwm_ao_d),
893 FUNCTION(jtag_ao),
894};
895
896static struct meson_bank meson_axg_periphs_banks[] = {
Carlo Caione139ebe92018-12-06 08:08:11 +0000897 /* name first last pullen pull dir out in */
898 BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
899 BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
900 BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
901 BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
902 BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
Jerome Brunet85878392018-10-05 09:36:37 +0200903};
904
905static struct meson_bank meson_axg_aobus_banks[] = {
Carlo Caione139ebe92018-12-06 08:08:11 +0000906 /* name first last pullen pull dir out in */
907 BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
Jerome Brunet85878392018-10-05 09:36:37 +0200908};
909
910static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200911 /* name first last reg offset */
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200912 BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0),
913 BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0),
914 BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0),
915 BANK_PMX("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 0x4, 0),
916 BANK_PMX("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 0x8, 0),
Jerome Brunet85878392018-10-05 09:36:37 +0200917};
918
919static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
920 .pmx_banks = meson_axg_periphs_pmx_banks,
921 .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
922};
923
924static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
925 BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
926};
927
928static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
929 .pmx_banks = meson_axg_aobus_pmx_banks,
930 .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
931};
932
933struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
934 .name = "periphs-banks",
Guillaume La Roque2c4e3cf2019-04-08 10:09:49 +0200935 .pin_base = EE_OFF,
Jerome Brunet85878392018-10-05 09:36:37 +0200936 .groups = meson_axg_periphs_groups,
937 .funcs = meson_axg_periphs_functions,
938 .banks = meson_axg_periphs_banks,
Carlo Caione139ebe92018-12-06 08:08:11 +0000939 .num_pins = 86,
Jerome Brunet85878392018-10-05 09:36:37 +0200940 .num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
941 .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
942 .num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
943 .gpio_driver = &meson_axg_gpio_driver,
944 .pmx_data = &meson_axg_periphs_pmx_banks_data,
945};
946
947struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
948 .name = "aobus-banks",
949 .pin_base = 0,
950 .groups = meson_axg_aobus_groups,
951 .funcs = meson_axg_aobus_functions,
952 .banks = meson_axg_aobus_banks,
953 .num_pins = 14,
954 .num_groups = ARRAY_SIZE(meson_axg_aobus_groups),
955 .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions),
956 .num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
957 .gpio_driver = &meson_axg_gpio_driver,
958 .pmx_data = &meson_axg_aobus_pmx_banks_data,
959};
960
961static const struct udevice_id meson_axg_pinctrl_match[] = {
962 {
963 .compatible = "amlogic,meson-axg-periphs-pinctrl",
964 .data = (ulong)&meson_axg_periphs_pinctrl_data,
965 },
966 {
967 .compatible = "amlogic,meson-axg-aobus-pinctrl",
968 .data = (ulong)&meson_axg_aobus_pinctrl_data,
969 },
970 { /* sentinel */ }
971};
972
973U_BOOT_DRIVER(meson_axg_pinctrl) = {
974 .name = "meson-axg-pinctrl",
975 .id = UCLASS_PINCTRL,
976 .of_match = of_match_ptr(meson_axg_pinctrl_match),
977 .probe = meson_pinctrl_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700978 .priv_auto = sizeof(struct meson_pinctrl),
Jerome Brunet85878392018-10-05 09:36:37 +0200979 .ops = &meson_axg_pinctrl_ops,
980};