Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2014 Google, Inc |
| 4 | * Written by Simon Glass <sjg@chromium.org> |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <dm.h> |
| 9 | #include <fdtdec.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 11 | #include <pci.h> |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 12 | |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 13 | #define FDT_DEV_INFO_CELLS 4 |
| 14 | #define FDT_DEV_INFO_SIZE (FDT_DEV_INFO_CELLS * sizeof(u32)) |
| 15 | |
| 16 | #define SANDBOX_PCI_DEVFN(d, f) ((d << 3) | f) |
| 17 | |
| 18 | struct sandbox_pci_priv { |
| 19 | struct { |
| 20 | u16 vendor; |
| 21 | u16 device; |
| 22 | } vendev[256]; |
| 23 | }; |
| 24 | |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 25 | static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn, |
| 26 | uint offset, ulong value, |
| 27 | enum pci_size_t size) |
| 28 | { |
| 29 | struct dm_pci_emul_ops *ops; |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 30 | struct udevice *container, *emul; |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 31 | int ret; |
| 32 | |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 33 | ret = sandbox_pci_get_emul(bus, devfn, &container, &emul); |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 34 | if (ret) |
| 35 | return ret == -ENODEV ? 0 : ret; |
| 36 | ops = pci_get_emul_ops(emul); |
| 37 | if (!ops || !ops->write_config) |
| 38 | return -ENOSYS; |
| 39 | |
| 40 | return ops->write_config(emul, offset, value, size); |
| 41 | } |
| 42 | |
Simon Glass | c4e72c4 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 43 | static int sandbox_pci_read_config(const struct udevice *bus, pci_dev_t devfn, |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 44 | uint offset, ulong *valuep, |
| 45 | enum pci_size_t size) |
| 46 | { |
| 47 | struct dm_pci_emul_ops *ops; |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 48 | struct udevice *container, *emul; |
| 49 | struct sandbox_pci_priv *priv = dev_get_priv(bus); |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 50 | int ret; |
| 51 | |
| 52 | /* Prepare the default response */ |
| 53 | *valuep = pci_get_ff(size); |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 54 | ret = sandbox_pci_get_emul(bus, devfn, &container, &emul); |
| 55 | if (ret) { |
| 56 | if (!container) { |
| 57 | u16 vendor, device; |
| 58 | |
| 59 | devfn = SANDBOX_PCI_DEVFN(PCI_DEV(devfn), |
| 60 | PCI_FUNC(devfn)); |
| 61 | vendor = priv->vendev[devfn].vendor; |
| 62 | device = priv->vendev[devfn].device; |
| 63 | if (offset == PCI_VENDOR_ID && vendor) |
| 64 | *valuep = vendor; |
| 65 | else if (offset == PCI_DEVICE_ID && device) |
| 66 | *valuep = device; |
| 67 | |
| 68 | return 0; |
| 69 | } else { |
| 70 | return ret == -ENODEV ? 0 : ret; |
| 71 | } |
| 72 | } |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 73 | ops = pci_get_emul_ops(emul); |
| 74 | if (!ops || !ops->read_config) |
| 75 | return -ENOSYS; |
| 76 | |
| 77 | return ops->read_config(emul, offset, valuep, size); |
| 78 | } |
| 79 | |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 80 | static int sandbox_pci_probe(struct udevice *dev) |
| 81 | { |
| 82 | struct sandbox_pci_priv *priv = dev_get_priv(dev); |
| 83 | const fdt32_t *cell; |
| 84 | u8 pdev, pfn, devfn; |
| 85 | int len; |
| 86 | |
| 87 | cell = ofnode_get_property(dev_ofnode(dev), "sandbox,dev-info", &len); |
| 88 | if (!cell) |
| 89 | return 0; |
| 90 | |
| 91 | if ((len % FDT_DEV_INFO_SIZE) == 0) { |
| 92 | int num = len / FDT_DEV_INFO_SIZE; |
| 93 | int i; |
| 94 | |
| 95 | for (i = 0; i < num; i++) { |
| 96 | debug("dev info #%d: %02x %02x %04x %04x\n", i, |
| 97 | fdt32_to_cpu(cell[0]), fdt32_to_cpu(cell[1]), |
| 98 | fdt32_to_cpu(cell[2]), fdt32_to_cpu(cell[3])); |
| 99 | |
| 100 | pdev = fdt32_to_cpu(cell[0]); |
| 101 | pfn = fdt32_to_cpu(cell[1]); |
| 102 | if (pdev > 31 || pfn > 7) |
| 103 | continue; |
| 104 | devfn = SANDBOX_PCI_DEVFN(pdev, pfn); |
| 105 | priv->vendev[devfn].vendor = fdt32_to_cpu(cell[2]); |
| 106 | priv->vendev[devfn].device = fdt32_to_cpu(cell[3]); |
| 107 | |
| 108 | cell += FDT_DEV_INFO_CELLS; |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 115 | static const struct dm_pci_ops sandbox_pci_ops = { |
| 116 | .read_config = sandbox_pci_read_config, |
| 117 | .write_config = sandbox_pci_write_config, |
| 118 | }; |
| 119 | |
| 120 | static const struct udevice_id sandbox_pci_ids[] = { |
| 121 | { .compatible = "sandbox,pci" }, |
| 122 | { } |
| 123 | }; |
| 124 | |
| 125 | U_BOOT_DRIVER(pci_sandbox) = { |
| 126 | .name = "pci_sandbox", |
| 127 | .id = UCLASS_PCI, |
| 128 | .of_match = sandbox_pci_ids, |
| 129 | .ops = &sandbox_pci_ops, |
Bin Meng | 4345998 | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 130 | .probe = sandbox_pci_probe, |
| 131 | .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv), |
Simon Glass | 9119548 | 2016-07-05 17:10:10 -0600 | [diff] [blame] | 132 | |
| 133 | /* Attach an emulator if we can */ |
| 134 | .child_post_bind = dm_scan_fdt_dev, |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 135 | .per_child_platdata_auto_alloc_size = |
| 136 | sizeof(struct pci_child_platdata), |
| 137 | }; |