| Mingkai Hu | dd02936 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 1 | Overview |
| 2 | -------- |
| 3 | The LS1046A Reference Design Board (RDB) is a high-performance computing, |
| 4 | evaluation, and development platform that supports the QorIQ LS1046A |
| 5 | LayerScape Architecture processor. The LS1046ARDB provides SW development |
| 6 | platform for the Freescale LS1046A processor series, with a complete |
| 7 | debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. |
| 8 | |
| 9 | LS1046A SoC Overview |
| 10 | -------------------- |
| 11 | Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A |
| 12 | SoC overview. |
| 13 | |
| 14 | LS1046ARDB board Overview |
| 15 | ----------------------- |
| 16 | - SERDES1 Connections, 4 lanes supporting: |
| 17 | - Lane0: XFI with x1 RJ45 connector |
| 18 | - Lane1: XFI Cage |
| 19 | - Lane2: SGMII.5 |
| 20 | - Lane3: SGMII.6 |
| 21 | - SERDES2 Connections, 4 lanes supporting: |
| 22 | - Lane0: PCIe1 with miniPCIe slot |
| 23 | - Lane1: PCIe2 with PCIe x2 slot |
| 24 | - Lane2: PCIe3 with PCIe x4 slot |
| 25 | - Lane3: SATA |
| 26 | - DDR Controller |
| 27 | - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s |
| 28 | -IFC/Local Bus |
| 29 | - One 512 MB NAND flash with ECC support |
| 30 | - CPLD connection |
| 31 | - USB 3.0 |
| 32 | - one Type A port, one Micro-AB port |
| 33 | - SDHC: connects directly to a full SD/MMC slot |
| 34 | - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) |
| 35 | - 4 I2C controllers |
| 36 | - UART |
| 37 | - Two 4-pin serial ports at up to 115.2 Kbit/s |
| 38 | - Two DB9 D-Type connectors supporting one Serial port each |
| 39 | - ARM JTAG support |
| 40 | |
| 41 | Memory map from core's view |
| 42 | ---------------------------- |
| 43 | Start Address End Address Description Size |
| 44 | 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB |
| 45 | 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB |
| 46 | 0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB |
| 47 | 0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB |
| 48 | 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB |
| 49 | 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB |
| 50 | 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB |
| 51 | 0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB |
| 52 | 0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M |
| 53 | 0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M |
| 54 | 0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB |
| 55 | 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G |
| 56 | 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G |
| 57 | 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G |
| 58 | |
| 59 | QSPI flash map: |
| 60 | Start Address End Address Description Size |
| 61 | 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB |
| 62 | 0x00_4010_0000 - 0x00_401F_FFFF U-Boot 1MB |
| 63 | 0x00_4020_0000 - 0x00_402F_FFFF U-Boot Env 1MB |
| 64 | 0x00_4030_0000 - 0x00_403F_FFFF FMan ucode 1MB |
| 65 | 0x00_4040_0000 - 0x00_404F_FFFF UEFI 1MB |
| 66 | 0x00_4050_0000 - 0x00_406F_FFFF PPA 2MB |
| 67 | 0x00_4070_0000 - 0x00_408F_FFFF Secure boot header |
| 68 | + bootscript 2MB |
| 69 | 0x00_4090_0000 - 0x00_40FF_FFFF Reserved 7MB |
| 70 | 0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB |
| 71 | |
| 72 | Booting Options |
| 73 | --------------- |
| 74 | a) QSPI boot |
| 75 | b) SD boot |
| 76 | c) eMMC boot |