Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a53e65d053401fff12740a8bbed8cb41670c268f / . / board / keymile / kmp204x / tlb.c
blob: d03ca802a442183f2bdc54c0673ed77d0ccdb22f [file] [log] [blame]
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200[diff] [blame]1/*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
14#include <asm/mmu.h>
15
16struct fsl_e_tlb_entry tlb_table[] = {
17 /* TLB 0 - for temp stack in cache */
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
19 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
20 MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
23 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
24 MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
28 MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
30 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
31 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
32 MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 /* TLB 1 */
35 /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
36 * SRAM is at 0xfff00000, it covered the 0xfffff000.
37 */
38 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 0, BOOKE_PAGESZ_1M, 1),
41
42 /* *I*G* - CCSRBAR */
43 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
44 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
45 0, 1, BOOKE_PAGESZ_16M, 1),
46 /* QRIO */
47 SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
48 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
49 0, 2, BOOKE_PAGESZ_64K, 1),
50 /* *I*G* - PCI1 */
51 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
52 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
53 0, 3, BOOKE_PAGESZ_512M, 1),
54 /* *I*G* - PCI3 */
55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
56 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 4, BOOKE_PAGESZ_512M, 1),
58 /* *I*G* - PCI1&3 I/O */
59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
60 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
61 0, 6, BOOKE_PAGESZ_128K, 1),
62#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
63 /* LBAPP1 */
64 SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
65 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
66 0, 7, BOOKE_PAGESZ_256M, 1),
67#endif
68#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
69 /* LBAPP2 */
70 SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
71 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
72 0, 8, BOOKE_PAGESZ_256M, 1),
73#endif
74 /* Bman/Qman */
75#ifdef CONFIG_SYS_BMAN_MEM_PHYS
76 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
77 MAS3_SW|MAS3_SR, 0,
78 0, 9, BOOKE_PAGESZ_1M, 1),
79 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
80 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
81 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 0, 10, BOOKE_PAGESZ_1M, 1),
83#endif
84#ifdef CONFIG_SYS_QMAN_MEM_PHYS
85 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
86 MAS3_SW|MAS3_SR, 0,
87 0, 11, BOOKE_PAGESZ_1M, 1),
88 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
89 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
90 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
91 0, 12, BOOKE_PAGESZ_1M, 1),
92#endif
93#ifdef CONFIG_SYS_DCSRBAR_PHYS
94 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
95 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
96 0, 13, BOOKE_PAGESZ_4M, 1),
97#endif
98#ifdef CONFIG_SYS_NAND_BASE
99 /*
100 * *I*G - NAND
101 * entry 14 and 15 has been used hard coded, they will be disabled
102 * in cpu_init_f, so we use entry 16 for nand.
103 */
104 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
105 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
106 0, 16, BOOKE_PAGESZ_32K, 1),
107#endif
108};
109
110int num_tlb_entries = ARRAY_SIZE(tlb_table);