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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
2 * board/mx1ads/mx1ads.c
wdenk49822e22004-06-19 21:19:10 +00003 *
wdenk2d24a3a2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
wdenk2d24a3a2004-06-09 21:50:45 +000026#include <common.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070027#include <netdev.h>
wdenk281e00a2004-08-01 22:48:16 +000028/*#include <mc9328.h>*/
wdenk86c98882005-04-03 14:26:46 +000029#include <asm/arch/imx-regs.h>
wdenk2d24a3a2004-06-09 21:50:45 +000030
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
wdenk2d24a3a2004-06-09 21:50:45 +000032
33#define FCLK_SPEED 1
34
35#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
36#define M_MDIV 0xC3
37#define M_PDIV 0x4
38#define M_SDIV 0x1
39#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
40#define M_MDIV 0xA1
41#define M_PDIV 0x3
42#define M_SDIV 0x1
43#endif
44
45#define USB_CLOCK 1
46
47#if USB_CLOCK==0
48#define U_M_MDIV 0xA1
49#define U_M_PDIV 0x3
50#define U_M_SDIV 0x1
51#elif USB_CLOCK==1
52#define U_M_MDIV 0x48
53#define U_M_PDIV 0x3
54#define U_M_SDIV 0x2
55#endif
56
57#if 0
58
Wolfgang Denkd87080b2006-03-31 18:32:53 +020059static inline void delay (unsigned long loops)
60{
wdenk2d24a3a2004-06-09 21:50:45 +000061 __asm__ volatile ("1:\n"
Wolfgang Denkd87080b2006-03-31 18:32:53 +020062 "subs %0, %1, #1\n"
63 "bne 1b":"=r" (loops):"0" (loops));
wdenk2d24a3a2004-06-09 21:50:45 +000064}
65
wdenk49822e22004-06-19 21:19:10 +000066#endif
wdenk2d24a3a2004-06-09 21:50:45 +000067
68/*
69 * Miscellaneous platform dependent initialisations
70 */
71
Wolfgang Denkd87080b2006-03-31 18:32:53 +020072void SetAsynchMode (void)
73{
74 __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
75 "mov r2, #0xC0000000 \n"
76 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
wdenk2d24a3a2004-06-09 21:50:45 +000077}
wdenk49822e22004-06-19 21:19:10 +000078
wdenk2d24a3a2004-06-09 21:50:45 +000079static u32 mc9328sid;
80
Fabio Estevame845f902011-06-11 15:16:32 +000081int board_early_init_f(void)
Wolfgang Denkd87080b2006-03-31 18:32:53 +020082{
83 volatile unsigned int tmp;
wdenk2d24a3a2004-06-09 21:50:45 +000084
Wolfgang Denkd87080b2006-03-31 18:32:53 +020085 mc9328sid = SIDR;
wdenk2d24a3a2004-06-09 21:50:45 +000086
Wolfgang Denkd87080b2006-03-31 18:32:53 +020087 GPCR = 0x000003AB; /* I/O pad driving strength */
wdenk2d24a3a2004-06-09 21:50:45 +000088
Wolfgang Denk53677ef2008-05-20 16:00:29 +020089 /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
90/* MX1_CS1L = 0x11110601; */
wdenk2d24a3a2004-06-09 21:50:45 +000091
Wolfgang Denkd87080b2006-03-31 18:32:53 +020092 MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
wdenk2d24a3a2004-06-09 21:50:45 +000093
94/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
95 * BCLK divider to 2 (i.e. BCLK to 48 MHz)
96 */
Wolfgang Denkd87080b2006-03-31 18:32:53 +020097 CSCR = 0xAF000403;
wdenk2d24a3a2004-06-09 21:50:45 +000098
Wolfgang Denkd87080b2006-03-31 18:32:53 +020099 CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
100 CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
wdenk2d24a3a2004-06-09 21:50:45 +0000101
102/* setup cs4 for cs8900 ethernet */
wdenk49822e22004-06-19 21:19:10 +0000103
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200104 CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
105 CS4L = 0x00001501;
wdenk49822e22004-06-19 21:19:10 +0000106
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200107 GIUS (0) &= 0xFF3FFFFF;
108 GPR (0) &= 0xFF3FFFFF;
wdenk49822e22004-06-19 21:19:10 +0000109
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200110 tmp = *(unsigned int *) (0x1500000C);
111 tmp = *(unsigned int *) (0x1500000C);
wdenk2d24a3a2004-06-09 21:50:45 +0000112
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200113 SetAsynchMode ();
wdenk2d24a3a2004-06-09 21:50:45 +0000114
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200115 icache_enable ();
116 dcache_enable ();
wdenk2d24a3a2004-06-09 21:50:45 +0000117
118/* set PERCLKs */
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200119 PCDR = 0x00000055; /* set PERCLKS */
wdenk49822e22004-06-19 21:19:10 +0000120
121/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
122 * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
wdenk2d24a3a2004-06-09 21:50:45 +0000123 * all sources selected as normal interrupt
124 */
wdenk2d24a3a2004-06-09 21:50:45 +0000125
wdenk281e00a2004-08-01 22:48:16 +0000126/* MX1_INTTYPEH = 0;
127 MX1_INTTYPEL = 0;
128*/
wdenk2d24a3a2004-06-09 21:50:45 +0000129 return 0;
130}
131
Fabio Estevame845f902011-06-11 15:16:32 +0000132int board_init(void)
133{
134 gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
135
136 gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
137
138 return 0;
139}
140
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200141int board_late_init (void)
142{
wdenk2d24a3a2004-06-09 21:50:45 +0000143
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200144 setenv ("stdout", "serial");
145 setenv ("stderr", "serial");
wdenk2d24a3a2004-06-09 21:50:45 +0000146
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200147 switch (mc9328sid) {
148 case 0x0005901d:
149 printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
150 mc9328sid);
151 break;
152 case 0x04d4c01d:
153 printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
154 mc9328sid);
155 break;
156 case 0x00d4c01d:
157 printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
158 mc9328sid);
159 break;
wdenk2d24a3a2004-06-09 21:50:45 +0000160
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200161 default:
162 printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
163 mc9328sid);
164 break;
wdenk2d24a3a2004-06-09 21:50:45 +0000165 }
wdenk2d24a3a2004-06-09 21:50:45 +0000166 return 0;
wdenk49822e22004-06-19 21:19:10 +0000167}
168
Fabio Estevame845f902011-06-11 15:16:32 +0000169int dram_init(void)
170{
171 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000172 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
Fabio Estevame845f902011-06-11 15:16:32 +0000173 PHYS_SDRAM_1_SIZE);
174 return 0;
175}
176
177void dram_init_banksize(void)
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200178{
wdenk2d24a3a2004-06-09 21:50:45 +0000179 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200180 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
wdenk2d24a3a2004-06-09 21:50:45 +0000181}
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700182
183#ifdef CONFIG_CMD_NET
184int board_eth_init(bd_t *bis)
185{
186 int rc = 0;
187#ifdef CONFIG_CS8900
188 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
189#endif
190 return rc;
191}
192#endif