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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a593c1fec579ea2e23ace4f06b06d8c168db2d05 / . / board / davinci / da8xxevm / u-boot-spl-da850evm.lds
blob: 7e0f09f3b5b17478a5883c648619e1cc76daff4f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
5 *
6 * (C) Copyright 2008
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]8 */
9
Tom Rini2f41ade2019-01-22 17:09:26 -0500[diff] [blame]10MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000[diff] [blame]11 LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]12
Adam Ford15b8c752019-02-25 21:53:46 -0600[diff] [blame]13MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
Tom Rini9b5f9ae2022-05-19 15:09:22 -0400[diff] [blame]14 LENGTH = 0x1080000 }
Adam Ford15b8c752019-02-25 21:53:46 -0600[diff] [blame]15
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]16OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
17OUTPUT_ARCH(arm)
18ENTRY(_start)
19SECTIONS
20{
21 . = 0x00000000;
22
23 . = ALIGN(4);
24 .text :
25 {
26 __start = .;
Benoît Thébaudeaueeadd3f2014-08-21 15:43:11 +0200[diff] [blame]27 *(.vectors)
Benoît Thébaudeau1a9a91d2013-04-11 09:36:03 +0000[diff] [blame]28 arch/arm/cpu/arm926ejs/start.o (.text*)
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]29 *(.text*)
30 } >.sram
31
32 . = ALIGN(4);
33 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
34
35 . = ALIGN(4);
36 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
Marek Vasut55675142012-10-12 10:27:03 +0000[diff] [blame]37
38 . = ALIGN(4);
Andrew Scull99e2fbc2022-05-30 10:00:04 +0000[diff] [blame]39 __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); } >.sram
Fabien Parent5d7cdf32016-11-29 14:23:40 +0100[diff] [blame]40
41 . = ALIGN(4);
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]42 .rel.dyn : {
43 __rel_dyn_start = .;
44 *(.rel*)
45 __rel_dyn_end = .;
46 } >.sram
47
Adam Ford15b8c752019-02-25 21:53:46 -0600[diff] [blame]48 __image_copy_end = .;
49
50 .end :
51 {
52 *(.__end)
53 }
54
55 _image_binary_end = .;
56
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]57 .bss :
58 {
59 . = ALIGN(4);
60 __bss_start = .;
61 *(.bss*)
62 . = ALIGN(4);
Simon Glass3929fb02013-03-14 06:54:53 +0000[diff] [blame]63 __bss_end = .;
Adam Ford15b8c752019-02-25 21:53:46 -0600[diff] [blame]64 } >.sdram
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000[diff] [blame]65}