blob: 951cbc4f57cfe701b7a812176fe8ebe7dc5de0be [file] [log] [blame]
Shengzhou Liuaba80042014-11-24 17:11:55 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 QDS board configuration file
9 */
10
11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14/* High Level Configuration Options */
Shengzhou Liuaba80042014-11-24 17:11:55 +080015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_BOOKE
17#define CONFIG_E500 /* BOOKE e500 family */
18#define CONFIG_E500MC /* BOOKE e500mc family */
19#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20#define CONFIG_MP /* support multiple processors */
21#define CONFIG_PHYS_64BIT
22#define CONFIG_ENABLE_36BIT_PHYS
23
24#ifdef CONFIG_PHYS_64BIT
25#define CONFIG_ADDR_MAP 1
26#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
27#endif
28
29#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
30#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
31#define CONFIG_FSL_IFC /* Enable IFC Support */
32
33#define CONFIG_FSL_LAW /* Use common FSL init code */
34#define CONFIG_ENV_OVERWRITE
35
36#define CONFIG_DEEP_SLEEP
tang yuantian2c537642014-12-18 09:55:07 +080037#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liuaba80042014-11-24 17:11:55 +080038#define CONFIG_SILENT_CONSOLE
tang yuantian2c537642014-12-18 09:55:07 +080039#define CONFIG_BOARD_EARLY_INIT_F
40#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +080041
42#ifdef CONFIG_RAMBOOT_PBL
43#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
44#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
45#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
46#define CONFIG_SPL_ENV_SUPPORT
47#define CONFIG_SPL_SERIAL_SUPPORT
48#define CONFIG_SPL_FLUSH_IMAGE
49#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50#define CONFIG_SPL_LIBGENERIC_SUPPORT
51#define CONFIG_SPL_LIBCOMMON_SUPPORT
52#define CONFIG_SPL_I2C_SUPPORT
53#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
54#define CONFIG_FSL_LAW /* Use common FSL init code */
55#define CONFIG_SYS_TEXT_BASE 0x00201000
56#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
57#define CONFIG_SPL_PAD_TO 0x40000
58#define CONFIG_SPL_MAX_SIZE 0x28000
59#define RESET_VECTOR_OFFSET 0x27FFC
60#define BOOT_PAGE_OFFSET 0x27000
61#ifdef CONFIG_SPL_BUILD
62#define CONFIG_SPL_SKIP_RELOCATE
63#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65#define CONFIG_SYS_NO_FLASH
66#endif
67
68#ifdef CONFIG_NAND
69#define CONFIG_SPL_NAND_SUPPORT
70#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
71#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
72#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
73#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
74#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
75#define CONFIG_SPL_NAND_BOOT
76#endif
77
78#ifdef CONFIG_SPIFLASH
79#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
80#define CONFIG_SPL_SPI_SUPPORT
81#define CONFIG_SPL_SPI_FLASH_SUPPORT
82#define CONFIG_SPL_SPI_FLASH_MINIMAL
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
87#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
88#ifndef CONFIG_SPL_BUILD
89#define CONFIG_SYS_MPC85XX_NO_RESETVEC
90#endif
91#define CONFIG_SPL_SPI_BOOT
92#endif
93
94#ifdef CONFIG_SDCARD
95#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
96#define CONFIG_SPL_MMC_SUPPORT
97#define CONFIG_SPL_MMC_MINIMAL
98#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
99#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
100#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
101#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
102#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
103#ifndef CONFIG_SPL_BUILD
104#define CONFIG_SYS_MPC85XX_NO_RESETVEC
105#endif
106#define CONFIG_SPL_MMC_BOOT
107#endif
108
109#endif /* CONFIG_RAMBOOT_PBL */
110
111#ifndef CONFIG_SYS_TEXT_BASE
112#define CONFIG_SYS_TEXT_BASE 0xeff40000
113#endif
114
115#ifndef CONFIG_RESET_VECTOR_ADDRESS
116#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117#endif
118
119#ifndef CONFIG_SYS_NO_FLASH
120#define CONFIG_FLASH_CFI_DRIVER
121#define CONFIG_SYS_FLASH_CFI
122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123#endif
124
125/* PCIe Boot - Master */
126#define CONFIG_SRIO_PCIE_BOOT_MASTER
127/*
128 * for slave u-boot IMAGE instored in master memory space,
129 * PHYS must be aligned based on the SIZE
130 */
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
132#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
133#ifdef CONFIG_PHYS_64BIT
134#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
135#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
136#else
137#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
138#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
139#endif
140/*
141 * for slave UCODE and ENV instored in master memory space,
142 * PHYS must be aligned based on the SIZE
143 */
144#ifdef CONFIG_PHYS_64BIT
145#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
146#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
147#else
148#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
149#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
150#endif
151#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
152/* slave core release by master*/
153#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
154#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
155
156/* PCIe Boot - Slave */
157#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
158#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
159#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
161/* Set 1M boot space for PCIe boot */
162#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
163#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
164 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
165#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
166#define CONFIG_SYS_NO_FLASH
167#endif
168
169#if defined(CONFIG_SPIFLASH)
170#define CONFIG_SYS_EXTRA_ENV_RELOC
171#define CONFIG_ENV_IS_IN_SPI_FLASH
172#define CONFIG_ENV_SPI_BUS 0
173#define CONFIG_ENV_SPI_CS 0
174#define CONFIG_ENV_SPI_MAX_HZ 10000000
175#define CONFIG_ENV_SPI_MODE 0
176#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
178#define CONFIG_ENV_SECT_SIZE 0x10000
179#elif defined(CONFIG_SDCARD)
180#define CONFIG_SYS_EXTRA_ENV_RELOC
181#define CONFIG_ENV_IS_IN_MMC
182#define CONFIG_SYS_MMC_ENV_DEV 0
183#define CONFIG_ENV_SIZE 0x2000
184#define CONFIG_ENV_OFFSET (512 * 0x800)
185#elif defined(CONFIG_NAND)
186#define CONFIG_SYS_EXTRA_ENV_RELOC
187#define CONFIG_ENV_IS_IN_NAND
188#define CONFIG_ENV_SIZE 0x2000
189#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
190#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
191#define CONFIG_ENV_IS_IN_REMOTE
192#define CONFIG_ENV_ADDR 0xffe20000
193#define CONFIG_ENV_SIZE 0x2000
194#elif defined(CONFIG_ENV_IS_NOWHERE)
195#define CONFIG_ENV_SIZE 0x2000
196#else
197#define CONFIG_ENV_IS_IN_FLASH
198#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE 0x2000
200#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
201#endif
202
203
204#ifndef __ASSEMBLY__
205unsigned long get_board_sys_clk(void);
206unsigned long get_board_ddr_clk(void);
207#endif
208
209#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
210#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
211
212/*
213 * These can be toggled for performance analysis, otherwise use default.
214 */
215#define CONFIG_SYS_CACHE_STASHING
216#define CONFIG_BACKSIDE_L2_CACHE
217#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
218#define CONFIG_BTB /* toggle branch predition */
219#define CONFIG_DDR_ECC
220#ifdef CONFIG_DDR_ECC
221#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
222#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
223#endif
224
225#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
226#define CONFIG_SYS_MEMTEST_END 0x00400000
227#define CONFIG_SYS_ALT_MEMTEST
228#define CONFIG_PANIC_HANG /* do not reset board on panic */
229
230/*
231 * Config the L3 Cache as L3 SRAM
232 */
233#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
234#define CONFIG_SYS_L3_SIZE (256 << 10)
235#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
236#ifdef CONFIG_RAMBOOT_PBL
237#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
238#endif
239#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
240#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
241#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
242#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
243
244#ifdef CONFIG_PHYS_64BIT
245#define CONFIG_SYS_DCSRBAR 0xf0000000
246#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
247#endif
248
249/* EEPROM */
250#define CONFIG_ID_EEPROM
251#define CONFIG_SYS_I2C_EEPROM_NXID
252#define CONFIG_SYS_EEPROM_BUS_NUM 0
253#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
254#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
255#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
256#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
257
258/*
259 * DDR Setup
260 */
261#define CONFIG_VERY_BIG_RAM
262#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
263#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
264#define CONFIG_DIMM_SLOTS_PER_CTLR 1
265#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
266#define CONFIG_DDR_SPD
267#ifndef CONFIG_SYS_FSL_DDR4
268#define CONFIG_SYS_FSL_DDR3
269#endif
270
271#define CONFIG_SYS_SPD_BUS_NUM 0
272#define SPD_EEPROM_ADDRESS 0x51
273
274#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
275
276/*
277 * IFC Definitions
278 */
279#define CONFIG_SYS_FLASH_BASE 0xe0000000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282#else
283#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
284#endif
285
286#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
287#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
288 + 0x8000000) | \
289 CSPR_PORT_SIZE_16 | \
290 CSPR_MSEL_NOR | \
291 CSPR_V)
292#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
293#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
294 CSPR_PORT_SIZE_16 | \
295 CSPR_MSEL_NOR | \
296 CSPR_V)
297#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
298/* NOR Flash Timing Params */
299#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
300#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
301 FTIM0_NOR_TEADC(0x5) | \
302 FTIM0_NOR_TEAHC(0x5))
303#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
304 FTIM1_NOR_TRAD_NOR(0x1A) |\
305 FTIM1_NOR_TSEQRAD_NOR(0x13))
306#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
307 FTIM2_NOR_TCH(0x4) | \
308 FTIM2_NOR_TWPH(0x0E) | \
309 FTIM2_NOR_TWP(0x1c))
310#define CONFIG_SYS_NOR_FTIM3 0x0
311
312#define CONFIG_SYS_FLASH_QUIET_TEST
313#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
314
315#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
316#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
317#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
318#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
319
320#define CONFIG_SYS_FLASH_EMPTY_INFO
321#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
322 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
323#define CONFIG_FSL_QIXIS /* use common QIXIS code */
324#define QIXIS_BASE 0xffdf0000
325#ifdef CONFIG_PHYS_64BIT
326#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
327#else
328#define QIXIS_BASE_PHYS QIXIS_BASE
329#endif
330#define QIXIS_LBMAP_SWITCH 0x06
331#define QIXIS_LBMAP_MASK 0x0f
332#define QIXIS_LBMAP_SHIFT 0
333#define QIXIS_LBMAP_DFLTBANK 0x00
334#define QIXIS_LBMAP_ALTBANK 0x04
335#define QIXIS_RST_CTL_RESET 0x31
336#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
337#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
338#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
339#define QIXIS_RST_FORCE_MEM 0x01
340
341#define CONFIG_SYS_CSPR3_EXT (0xf)
342#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
343 | CSPR_PORT_SIZE_8 \
344 | CSPR_MSEL_GPCM \
345 | CSPR_V)
346#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
347#define CONFIG_SYS_CSOR3 0x0
348/* QIXIS Timing parameters for IFC CS3 */
349#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
350 FTIM0_GPCM_TEADC(0x0e) | \
351 FTIM0_GPCM_TEAHC(0x0e))
352#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
353 FTIM1_GPCM_TRAD(0x3f))
354#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
355 FTIM2_GPCM_TCH(0x8) | \
356 FTIM2_GPCM_TWP(0x1f))
357#define CONFIG_SYS_CS3_FTIM3 0x0
358
359#define CONFIG_NAND_FSL_IFC
360#define CONFIG_SYS_NAND_BASE 0xff800000
361#ifdef CONFIG_PHYS_64BIT
362#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
363#else
364#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
365#endif
366#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
367#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
368 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
369 | CSPR_MSEL_NAND /* MSEL = NAND */ \
370 | CSPR_V)
371#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
372
373#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
374 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
375 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
376 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
377 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
378 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
379 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
380
381#define CONFIG_SYS_NAND_ONFI_DETECTION
382
383/* ONFI NAND Flash mode0 Timing Params */
384#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
385 FTIM0_NAND_TWP(0x18) | \
386 FTIM0_NAND_TWCHT(0x07) | \
387 FTIM0_NAND_TWH(0x0a))
388#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
389 FTIM1_NAND_TWBE(0x39) | \
390 FTIM1_NAND_TRR(0x0e) | \
391 FTIM1_NAND_TRP(0x18))
392#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
393 FTIM2_NAND_TREH(0x0a) | \
394 FTIM2_NAND_TWHRE(0x1e))
395#define CONFIG_SYS_NAND_FTIM3 0x0
396
397#define CONFIG_SYS_NAND_DDR_LAW 11
398#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
399#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800400#define CONFIG_CMD_NAND
401
402#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
403
404#if defined(CONFIG_NAND)
405#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
406#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
407#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
408#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
409#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
410#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
411#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
412#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
413#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
414#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
415#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
416#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
417#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
418#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
419#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
420#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
421#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
422#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
423#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
424#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
425#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
426#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
427#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
428#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
429#else
430#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
431#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
432#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
433#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
434#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
435#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
436#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
437#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
438#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
439#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
440#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
441#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
442#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
443#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
444#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
445#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
446#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
447#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
448#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
449#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
450#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
451#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
452#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
453#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
454#endif
455
456#ifdef CONFIG_SPL_BUILD
457#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
458#else
459#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
460#endif
461
462#if defined(CONFIG_RAMBOOT_PBL)
463#define CONFIG_SYS_RAMBOOT
464#endif
465
466#define CONFIG_BOARD_EARLY_INIT_R
467#define CONFIG_MISC_INIT_R
468
469#define CONFIG_HWCONFIG
470
471/* define to use L1 as initial stack */
472#define CONFIG_L1_INIT_RAM
473#define CONFIG_SYS_INIT_RAM_LOCK
474#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
475#ifdef CONFIG_PHYS_64BIT
476#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700477#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuaba80042014-11-24 17:11:55 +0800478/* The assembler doesn't like typecast */
479#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
480 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
481 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
482#else
York Sunb3142e22015-08-17 13:31:51 -0700483#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800484#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
486#endif
487#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
488
489#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
490 GENERATED_GBL_DATA_SIZE)
491#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
492
493#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
494#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
495
496/* Serial Port */
497#define CONFIG_CONS_INDEX 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800498#define CONFIG_SYS_NS16550_SERIAL
499#define CONFIG_SYS_NS16550_REG_SIZE 1
500#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
501
502#define CONFIG_SYS_BAUDRATE_TABLE \
503 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
504
505#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
506#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
507#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
508#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
509#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
510
511/* Use the HUSH parser */
512#define CONFIG_SYS_HUSH_PARSER
513#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
514
515/* Video */
516#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
517#define CONFIG_FSL_DIU_FB
518#ifdef CONFIG_FSL_DIU_FB
519#define CONFIG_FSL_DIU_CH7301
520#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
521#define CONFIG_VIDEO
522#define CONFIG_CMD_BMP
523#define CONFIG_CFB_CONSOLE
524#define CONFIG_VIDEO_SW_CURSOR
525#define CONFIG_VGA_AS_SINGLE_DEVICE
526#define CONFIG_VIDEO_LOGO
527#define CONFIG_VIDEO_BMP_LOGO
528#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
529/*
530 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
531 * disable empty flash sector detection, which is I/O-intensive.
532 */
533#undef CONFIG_SYS_FLASH_EMPTY_INFO
534#endif
535#endif
536
537/* pass open firmware flat tree */
538#define CONFIG_OF_LIBFDT
539#define CONFIG_OF_BOARD_SETUP
540#define CONFIG_OF_STDOUT_VIA_ALIAS
541
542/* new uImage format support */
543#define CONFIG_FIT
544#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
545
546/* I2C */
547#define CONFIG_SYS_I2C
548#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
549#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
550#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
551#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
552#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
553#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
554#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
555
556#define I2C_MUX_PCA_ADDR 0x77
557#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800558#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
559#define I2C_RETIMER_ADDR 0x18
Shengzhou Liuaba80042014-11-24 17:11:55 +0800560
561/* I2C bus multiplexer */
562#define I2C_MUX_CH_DEFAULT 0x8
563#define I2C_MUX_CH_DIU 0xC
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800564#define I2C_MUX_CH5 0xD
565#define I2C_MUX_CH7 0xF
Shengzhou Liuaba80042014-11-24 17:11:55 +0800566
567/* LDI/DVI Encoder for display */
568#define CONFIG_SYS_I2C_LDI_ADDR 0x38
569#define CONFIG_SYS_I2C_DVI_ADDR 0x75
570
571/*
572 * RTC configuration
573 */
574#define RTC
575#define CONFIG_RTC_DS3231 1
576#define CONFIG_SYS_I2C_RTC_ADDR 0x68
577
578/*
579 * eSPI - Enhanced SPI
580 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800581#ifndef CONFIG_SPL_BUILD
Shengzhou Liuaba80042014-11-24 17:11:55 +0800582#endif
583#define CONFIG_CMD_SF
584#define CONFIG_SPI_FLASH_BAR
585#define CONFIG_SF_DEFAULT_SPEED 10000000
586#define CONFIG_SF_DEFAULT_MODE 0
587
588/*
589 * General PCIe
590 * Memory space is mapped 1-1, but I/O space must start from 0.
591 */
592#define CONFIG_PCI /* Enable PCI/PCIE */
593#define CONFIG_PCIE1 /* PCIE controler 1 */
594#define CONFIG_PCIE2 /* PCIE controler 2 */
595#define CONFIG_PCIE3 /* PCIE controler 3 */
596#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
597#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
598#define CONFIG_PCI_INDIRECT_BRIDGE
599
600#ifdef CONFIG_PCI
601/* controller 1, direct to uli, tgtid 3, Base address 20000 */
602#ifdef CONFIG_PCIE1
603#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
604#ifdef CONFIG_PHYS_64BIT
605#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
606#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
607#else
608#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
609#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
610#endif
611#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
612#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
613#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
614#ifdef CONFIG_PHYS_64BIT
615#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
616#else
617#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
618#endif
619#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
620#endif
621
622/* controller 2, Slot 2, tgtid 2, Base address 201000 */
623#ifdef CONFIG_PCIE2
624#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
625#ifdef CONFIG_PHYS_64BIT
626#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
627#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
628#else
629#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
630#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
631#endif
632#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
633#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
634#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
635#ifdef CONFIG_PHYS_64BIT
636#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
637#else
638#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
639#endif
640#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
641#endif
642
643/* controller 3, Slot 1, tgtid 1, Base address 202000 */
644#ifdef CONFIG_PCIE3
645#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
646#ifdef CONFIG_PHYS_64BIT
647#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
648#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
649#else
650#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
651#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
652#endif
653#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
654#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
655#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
656#ifdef CONFIG_PHYS_64BIT
657#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
658#else
659#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
660#endif
661#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
662#endif
663
664#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800665#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
666#define CONFIG_DOS_PARTITION
667#endif /* CONFIG_PCI */
668
669/*
670 *SATA
671 */
672#define CONFIG_FSL_SATA_V2
673#ifdef CONFIG_FSL_SATA_V2
674#define CONFIG_LIBATA
675#define CONFIG_FSL_SATA
676#define CONFIG_SYS_SATA_MAX_DEVICE 1
677#define CONFIG_SATA1
678#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
679#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
680#define CONFIG_LBA48
681#define CONFIG_CMD_SATA
682#define CONFIG_DOS_PARTITION
683#define CONFIG_CMD_EXT2
684#endif
685
686/*
687 * USB
688 */
689#define CONFIG_HAS_FSL_DR_USB
690
691#ifdef CONFIG_HAS_FSL_DR_USB
692#define CONFIG_USB_EHCI
693#define CONFIG_CMD_USB
694#define CONFIG_USB_STORAGE
695#define CONFIG_USB_EHCI_FSL
696#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
697#define CONFIG_CMD_EXT2
698#endif
699
700/*
701 * SDHC
702 */
703#define CONFIG_MMC
704#ifdef CONFIG_MMC
705#define CONFIG_FSL_ESDHC
706#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
707#define CONFIG_CMD_MMC
708#define CONFIG_GENERIC_MMC
709#define CONFIG_CMD_EXT2
710#define CONFIG_CMD_FAT
711#define CONFIG_DOS_PARTITION
712#endif
713
714/* Qman/Bman */
715#ifndef CONFIG_NOBQFMAN
716#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500717#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800718#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
719#ifdef CONFIG_PHYS_64BIT
720#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
721#else
722#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
723#endif
724#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500725#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
726#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
727#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
728#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
729#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
730 CONFIG_SYS_BMAN_CENA_SIZE)
731#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
732#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500733#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800734#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
735#ifdef CONFIG_PHYS_64BIT
736#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
737#else
738#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
739#endif
740#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500741#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
742#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
743#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
744#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
745#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
746 CONFIG_SYS_QMAN_CENA_SIZE)
747#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
748#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuaba80042014-11-24 17:11:55 +0800749
750#define CONFIG_SYS_DPAA_FMAN
751
752#define CONFIG_QE
753#define CONFIG_U_QE
754/* Default address of microcode for the Linux FMan driver */
755#if defined(CONFIG_SPIFLASH)
756/*
757 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
758 * env, so we got 0x110000.
759 */
760#define CONFIG_SYS_QE_FW_IN_SPIFLASH
761#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
762#define CONFIG_SYS_QE_FW_ADDR 0x130000
763#elif defined(CONFIG_SDCARD)
764/*
765 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
766 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
767 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
768 */
769#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
770#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
771#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
772#elif defined(CONFIG_NAND)
773#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
774#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
775#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
776#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
777/*
778 * Slave has no ucode locally, it can fetch this from remote. When implementing
779 * in two corenet boards, slave's ucode could be stored in master's memory
780 * space, the address can be mapped from slave TLB->slave LAW->
781 * slave SRIO or PCIE outbound window->master inbound window->
782 * master LAW->the ucode address in master's memory space.
783 */
784#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
785#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
786#else
787#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
788#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
789#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
790#endif
791#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
792#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
793#endif /* CONFIG_NOBQFMAN */
794
795#ifdef CONFIG_SYS_DPAA_FMAN
796#define CONFIG_FMAN_ENET
797#define CONFIG_PHYLIB_10G
798#define CONFIG_PHY_VITESSE
799#define CONFIG_PHY_REALTEK
800#define CONFIG_PHY_TERANETICS
801#define RGMII_PHY1_ADDR 0x1
802#define RGMII_PHY2_ADDR 0x2
803#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
804#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
805#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
806#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
807#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
808#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
809#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
810#endif
811
812#ifdef CONFIG_FMAN_ENET
813#define CONFIG_MII /* MII PHY management */
814#define CONFIG_ETHPRIME "FM1@DTSEC4"
815#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
816#endif
817
818/*
819 * Dynamic MTD Partition support with mtdparts
820 */
821#ifndef CONFIG_SYS_NO_FLASH
822#define CONFIG_MTD_DEVICE
823#define CONFIG_MTD_PARTITIONS
824#define CONFIG_CMD_MTDPARTS
825#define CONFIG_FLASH_CFI_MTD
826#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
827 "spi0=spife110000.0"
828#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
829 "128k(dtb),96m(fs),-(user);"\
830 "fff800000.flash:2m(uboot),9m(kernel),"\
831 "128k(dtb),96m(fs),-(user);spife110000.0:" \
832 "2m(uboot),9m(kernel),128k(dtb),-(user)"
833#endif
834
835/*
836 * Environment
837 */
838#define CONFIG_LOADS_ECHO /* echo on for serial download */
839#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
840
841/*
842 * Command line configuration.
843 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800844#define CONFIG_CMD_DATE
845#define CONFIG_CMD_DHCP
846#define CONFIG_CMD_EEPROM
Shengzhou Liuaba80042014-11-24 17:11:55 +0800847#define CONFIG_CMD_ERRATA
848#define CONFIG_CMD_GREPENV
849#define CONFIG_CMD_IRQ
850#define CONFIG_CMD_I2C
851#define CONFIG_CMD_MII
852#define CONFIG_CMD_PING
853#define CONFIG_CMD_REGINFO
Shengzhou Liuaba80042014-11-24 17:11:55 +0800854
855#ifdef CONFIG_PCI
856#define CONFIG_CMD_PCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800857#endif
858
859/*
860 * Miscellaneous configurable options
861 */
862#define CONFIG_SYS_LONGHELP /* undef to save memory */
863#define CONFIG_CMDLINE_EDITING /* Command-line editing */
864#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
865#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800866#ifdef CONFIG_CMD_KGDB
867#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
868#else
869#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
870#endif
871#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
872#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
873#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
874
875/*
876 * For booting Linux, the board info and command line data
877 * have to be in the first 64 MB of memory, since this is
878 * the maximum mapped by the Linux kernel during initialization.
879 */
880#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
881#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
882
883#ifdef CONFIG_CMD_KGDB
884#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
885#endif
886
887/*
888 * Environment Configuration
889 */
890#define CONFIG_ROOTPATH "/opt/nfsroot"
891#define CONFIG_BOOTFILE "uImage"
892#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
893#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
894#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
895#define CONFIG_BAUDRATE 115200
896#define __USB_PHY_TYPE utmi
897
898
899#define CONFIG_EXTRA_ENV_SETTINGS \
900 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
901 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
902 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
903 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
904 "fdtfile=t1024qds/t1024qds.dtb\0" \
905 "netdev=eth0\0" \
906 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
907 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
908 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
909 "tftpflash=tftpboot $loadaddr $uboot && " \
910 "protect off $ubootaddr +$filesize && " \
911 "erase $ubootaddr +$filesize && " \
912 "cp.b $loadaddr $ubootaddr $filesize && " \
913 "protect on $ubootaddr +$filesize && " \
914 "cmp.b $loadaddr $ubootaddr $filesize\0" \
915 "consoledev=ttyS0\0" \
916 "ramdiskaddr=2000000\0" \
917 "fdtaddr=d00000\0" \
918 "bdev=sda3\0"
919
920#define CONFIG_LINUX \
921 "setenv bootargs root=/dev/ram rw " \
922 "console=$consoledev,$baudrate $othbootargs;" \
923 "setenv ramdiskaddr 0x02000000;" \
924 "setenv fdtaddr 0x00c00000;" \
925 "setenv loadaddr 0x1000000;" \
926 "bootm $loadaddr $ramdiskaddr $fdtaddr"
927
928#define CONFIG_NFSBOOTCOMMAND \
929 "setenv bootargs root=/dev/nfs rw " \
930 "nfsroot=$serverip:$rootpath " \
931 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
932 "console=$consoledev,$baudrate $othbootargs;" \
933 "tftp $loadaddr $bootfile;" \
934 "tftp $fdtaddr $fdtfile;" \
935 "bootm $loadaddr - $fdtaddr"
936
937#define CONFIG_BOOTCOMMAND CONFIG_LINUX
938
939#ifdef CONFIG_SECURE_BOOT
940#include <asm/fsl_secure_boot.h>
941#endif
942
943#endif /* __T1024QDS_H */