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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
21#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf12e5682003-07-07 20:07:54 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf12e5682003-07-07 20:07:54 +000026#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020027#define CONFIG_SYS_SMC_RXBUFLEN 128
28#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000029#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
30
wdenkae3af052003-08-07 22:18:11 +000031#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000032
wdenkae3af052003-08-07 22:18:11 +000033#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000034
35#define CONFIG_BOARD_TYPES 1 /* support board types */
36
37#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010038 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000039 "echo"
40
41#undef CONFIG_BOOTARGS
42
43#define CONFIG_EXTRA_ENV_SETTINGS \
44 "netdev=eth0\0" \
45 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010046 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000047 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010048 "addip=setenv bootargs ${bootargs} " \
49 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
50 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000051 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000053 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
55 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000056 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020057 "hostname=TQM860M\0" \
58 "bootfile=TQM860M/uImage\0" \
Martin Krauseda3aad52007-09-26 17:55:56 +020059 "fdt_addr=400C0000\0" \
60 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020061 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020062 "u-boot=TQM860M/u-image.bin\0" \
Martin Krauseda3aad52007-09-26 17:55:56 +020063 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020064 "update=prot off 40000000 +${filesize};" \
65 "era 40000000 +${filesize};" \
Martin Krauseda3aad52007-09-26 17:55:56 +020066 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020067 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000068 ""
69#define CONFIG_BOOTCOMMAND "run flash_self"
70
71#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000073
74#undef CONFIG_WATCHDOG /* watchdog disabled */
75
76#define CONFIG_STATUS_LED 1 /* Status LED enabled */
77
78#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
79
Jon Loeliger37d4bb72007-07-09 21:38:02 -050080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88
wdenkf12e5682003-07-07 20:07:54 +000089
90#define CONFIG_MAC_PARTITION
91#define CONFIG_DOS_PARTITION
92
93#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
94
wdenkf12e5682003-07-07 20:07:54 +000095
Jon Loeliger26946902007-07-04 22:30:50 -050096/*
97 * Command line configuration.
98 */
Jon Loeliger26946902007-07-04 22:30:50 -050099#define CONFIG_CMD_ASKENV
100#define CONFIG_CMD_DATE
101#define CONFIG_CMD_DHCP
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100102#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500103#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200104#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500105#define CONFIG_CMD_SNTP
106
wdenkf12e5682003-07-07 20:07:54 +0000107
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200108#define CONFIG_NETCONSOLE
109
110
wdenkf12e5682003-07-07 20:07:54 +0000111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf12e5682003-07-07 20:07:54 +0000115
Wolfgang Denk2751a952006-10-28 02:29:14 +0200116#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000118
Jon Loeliger26946902007-07-04 22:30:50 -0500119#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000123#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000132
wdenkf12e5682003-07-07 20:07:54 +0000133/*
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
137 */
138/*-----------------------------------------------------------------------
139 * Internal Memory Mapped Register
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000142
143/*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200147#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200148#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000150
151/*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_SDRAM_BASE 0x00000000
157#define CONFIG_SYS_FLASH_BASE 0x40000000
158#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
160#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000161
162/*
163 * For booting Linux, the board info and command line data
164 * have to be in the first 8 MB of memory, since this is
165 * the maximum mapped by the Linux kernel during initialization.
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000168
169/*-----------------------------------------------------------------------
170 * FLASH organization
171 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200172/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200174#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
176#define CONFIG_SYS_FLASH_EMPTY_INFO
177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000180
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200181#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200182#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
183#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
184#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000185
186/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
188#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200191
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200192#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
193
wdenkf12e5682003-07-07 20:07:54 +0000194/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200195 * Dynamic MTD partition support
196 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100197#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200198#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
199#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200200#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
201
202#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
203 "128k(dtb)," \
204 "1920k(kernel)," \
205 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200206 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200207
208/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000209 * Hardware Information Block
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
212#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
213#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000214
215/*-----------------------------------------------------------------------
216 * Cache Configuration
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500219#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000221#endif
222
223/*-----------------------------------------------------------------------
224 * SYPCR - System Protection Control 11-9
225 * SYPCR can only be written once after reset!
226 *-----------------------------------------------------------------------
227 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 */
229#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000231 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000234#endif
235
236/*-----------------------------------------------------------------------
237 * SIUMCR - SIU Module Configuration 11-6
238 *-----------------------------------------------------------------------
239 * PCMCIA config., multi-function pin tri-state
240 */
241#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000243#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000245#endif /* CONFIG_CAN_DRIVER */
246
247/*-----------------------------------------------------------------------
248 * TBSCR - Time Base Status and Control 11-26
249 *-----------------------------------------------------------------------
250 * Clear Reference Interrupt Status, Timebase freezing enabled
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000253
254/*-----------------------------------------------------------------------
255 * RTCSC - Real-Time Clock Status and Control Register 11-27
256 *-----------------------------------------------------------------------
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000259
260/*-----------------------------------------------------------------------
261 * PISCR - Periodic Interrupt Status and Control 11-31
262 *-----------------------------------------------------------------------
263 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000266
267/*-----------------------------------------------------------------------
268 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
269 *-----------------------------------------------------------------------
270 * Reset PLL lock status sticky bit, timer expired status bit and timer
271 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000274
275/*-----------------------------------------------------------------------
276 * SCCR - System Clock and reset Control Register 15-27
277 *-----------------------------------------------------------------------
278 * Set clock output, timebase and RTC source and divider,
279 * power management and some other internal clocks
280 */
281#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000283 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
284 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000285
286/*-----------------------------------------------------------------------
287 * PCMCIA stuff
288 *-----------------------------------------------------------------------
289 *
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
292#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
293#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
294#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
295#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
296#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
297#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
298#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000299
300/*-----------------------------------------------------------------------
301 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
302 *-----------------------------------------------------------------------
303 */
304
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000305#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000306#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
307
308#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
309#undef CONFIG_IDE_LED /* LED for ide not supported */
310#undef CONFIG_IDE_RESET /* reset for ide not supported */
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
313#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000318
319/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000321
322/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000324
325/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000327
328/*-----------------------------------------------------------------------
329 *
330 *-----------------------------------------------------------------------
331 *
332 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000334
335/*
336 * Init Memory Controller:
337 *
338 * BR0/1 and OR0/1 (FLASH)
339 */
340
341#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
342#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
343
344/* used to re-map FLASH both when starting from SRAM or FLASH:
345 * restrict access enough to keep SRAM working (if any)
346 * but not too much to meddle with FLASH accesses
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
349#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000350
351/*
352 * FLASH timing:
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000355 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
358#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
359#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
362#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
363#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000364
365/*
366 * BR2/3 and OR2/3 (SDRAM)
367 *
368 */
369#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
370#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
Jens Gehrleindabad4b2007-09-27 14:54:46 +0200371#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
wdenkf12e5682003-07-07 20:07:54 +0000372
373/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
377#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000378
379#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
381#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000382#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
384#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
385#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
386#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000387 BR_PS_8 | BR_MS_UPMB | BR_V )
388#endif /* CONFIG_CAN_DRIVER */
389
390/*
391 * Memory Periodic Timer Prescaler
392 *
393 * The Divider for PTA (refresh timer) configuration is based on an
394 * example SDRAM configuration (64 MBit, one bank). The adjustment to
395 * the number of chip selects (NCS) and the actually needed refresh
396 * rate is done by setting MPTPR.
397 *
398 * PTA is calculated from
399 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
400 *
401 * gclk CPU clock (not bus clock!)
402 * Trefresh Refresh cycle * 4 (four word bursts used)
403 *
404 * 4096 Rows from SDRAM example configuration
405 * 1000 factor s -> ms
406 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
407 * 4 Number of refresh cycles per period
408 * 64 Refresh cycle in ms per number of rows
409 * --------------------------------------------
410 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
411 *
412 * 50 MHz => 50.000.000 / Divider = 98
413 * 66 Mhz => 66.000.000 / Divider = 129
414 * 80 Mhz => 80.000.000 / Divider = 156
415 */
wdenke9132ea2004-04-24 23:23:30 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
418#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000419
420/*
421 * For 16 MBit, refresh rates could be 31.3 us
422 * (= 64 ms / 2K = 125 / quad bursts).
423 * For a simpler initialization, 15.6 us is used instead.
424 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
426 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000427 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
429#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000430
431/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
433#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000434
435/*
436 * MAMR settings for SDRAM
437 */
438
439/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000441 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
442 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
443/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000445 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
446 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
Jens Gehrleindabad4b2007-09-27 14:54:46 +0200447/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Jens Gehrleindabad4b2007-09-27 14:54:46 +0200449 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
450 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkf12e5682003-07-07 20:07:54 +0000451
wdenkf12e5682003-07-07 20:07:54 +0000452#define CONFIG_SCC1_ENET
453#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200454#define CONFIG_ETHPRIME "SCC"
wdenkf12e5682003-07-07 20:07:54 +0000455
Heiko Schocher7026ead2010-02-09 15:50:27 +0100456/* pass open firmware flat tree */
457#define CONFIG_OF_LIBFDT 1
458#define CONFIG_OF_BOARD_SETUP 1
459#define CONFIG_HWCONFIG 1
460
wdenkf12e5682003-07-07 20:07:54 +0000461#endif /* __CONFIG_H */