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Michal Simek18a952c2018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simek1f4f3d32016-04-07 15:58:23 +02002/*
3 * dts file for Xilinx ZynqMP ZCU102 RevB
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2016 - 2020, Xilinx, Inc.
Michal Simek1f4f3d32016-04-07 15:58:23 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simek1f4f3d32016-04-07 15:58:23 +02008 */
9
Michal Simekbe463452017-07-20 12:38:27 +020010#include "zynqmp-zcu102-revA.dts"
Michal Simek1f4f3d32016-04-07 15:58:23 +020011
12/ {
13 model = "ZynqMP ZCU102 RevB";
Michal Simek582ee922017-11-02 10:22:27 +010014 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Michal Simek1f4f3d32016-04-07 15:58:23 +020015};
16
17&gem3 {
18 phy-handle = <&phyc>;
Michal Simek2975a422019-08-08 12:44:22 +020019 phyc: ethernet-phy@c {
Michal Simek1f4f3d32016-04-07 15:58:23 +020020 reg = <0xc>;
21 ti,rx-internal-delay = <0x8>;
22 ti,tx-internal-delay = <0xa>;
23 ti,fifo-depth = <0x1>;
Harini Katakam631d9a92019-02-13 17:02:21 +053024 ti,dp83867-rxctrl-strap-quirk;
Harini Katakam26b2c682019-03-13 19:41:19 +053025 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
Michal Simek1f4f3d32016-04-07 15:58:23 +020026 };
27 /* Cleanup from RevA */
Michal Simek32da5352020-01-09 13:01:07 +010028 /delete-node/ ethernet-phy@21;
Michal Simek1f4f3d32016-04-07 15:58:23 +020029};
30
Michal Simek1f4f3d32016-04-07 15:58:23 +020031/* Fix collision with u61 */
32&i2c0 {
Michal Simekba7b6df2018-03-27 10:38:08 +020033 i2c-mux@75 {
Michal Simek1f4f3d32016-04-07 15:58:23 +020034 i2c@2 {
35 max15303@1b { /* u8 */
Michal Simeka16e5782018-03-27 10:52:40 +020036 compatible = "maxim,max15303";
Michal Simek1f4f3d32016-04-07 15:58:23 +020037 reg = <0x1b>;
38 };
39 /delete-node/ max15303@20;
40 };
41 };
42};