blob: b2ea5ce0d8a3424e831e4360056b61df363c0958 [file] [log] [blame]
Bartlomiej Sieka86b116b2007-08-03 12:08:16 +02001/*
2 * (C) Copyright 2007 DENX Software Engineering
3 *
4 * Author: Bartlomiej Sieka <tur@semihalf.com>
5 * Author: Grzegorz Bernacki <gjb@semihalf.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef _CM5200_H
24#define _CM5200_H
25
26
27/*
28 * Definitions and declarations for the modules of the cm5200 platform. Mostly
29 * related to reading the hardware identification data (HW ID) from the I2C
30 * EEPROM, detection of the particular module we are executing on, and
31 * appropriate SDRAM controller initialization.
32 */
33
34
35#define CM5200_UNKNOWN_MODULE 0xffffffff
36
37enum {
38 DEVICE_NAME, /* 0 */
39 GENERATION, /* 1 */
40 PCB_NAME, /* 2 */
41 FORM, /* 3 */
42 VERSION, /* 4 */
43 IDENTIFICATION_NUMBER, /* 5 */
44 MAJOR_SW_VERSION, /* 6 */
45 MINOR_SW_VERSION, /* 7 */
46 /* add new alements above this line */
47 HW_ID_ELEM_COUNT /* count */
48};
49
50/*
51 * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
52 */
53
54#define DEVICE_NAME_OFFSET 0x02
55#define GENERATION_OFFSET 0x0b
56#define PCB_NAME_OFFSET 0x0c
57#define FORM_OFFSET 0x15
58#define VERSION_OFFSET 0x16
59#define IDENTIFICATION_NUMBER_OFFSET 0x19
60#define MAJOR_SW_VERSION_OFFSET 0x0480
61#define MINOR_SW_VERSION_OFFSET 0x0481
62
63
64#define DEVICE_NAME_LEN 0x09
65#define GENERATION_LEN 0x01
66#define PCB_NAME_LEN 0x09
67#define FORM_LEN 0x01
68#define VERSION_LEN 0x03
69#define IDENTIFICATION_NUMBER_LEN 0x09
70#define MAJOR_SW_VERSION_LEN 0x01
71#define MINOR_SW_VERSION_LEN 0x01
72
73#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
74
75/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
76#define MODULE_NAME_MAXLEN 64
77
78
79/* storage for HW ID read from EEPROM */
80typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
81
82
83/* HW ID layout in EEPROM */
84static struct {
85 unsigned int offset;
86 unsigned int length;
87} hw_id_format[HW_ID_ELEM_COUNT] = {
88 {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
89 {GENERATION_OFFSET, GENERATION_LEN},
90 {PCB_NAME_OFFSET, PCB_NAME_LEN},
91 {FORM_OFFSET, FORM_LEN},
92 {VERSION_OFFSET, VERSION_LEN},
93 {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
94 {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
95 {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
96};
97
98
99/* HW ID data found in EEPROM on supported modules */
100static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
101 "CM", /* DEVICE_NAME */
102 "1", /* GENERATION */
103 "CM1", /* PCB_NAME */
104 "Q", /* FORM */
105 "A", /* VERSION */
106 "591881", /* IDENTIFICATION_NUMBER */
107 "", /* MAJOR_SW_VERSION */
108 "", /* MINOR_SW_VERSION */
109};
110
111static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
112 "CM", /* DEVICE_NAME */
113 "1", /* GENERATION */
114 "CM11", /* PCB_NAME */
115 "Q", /* FORM */
116 "A", /* VERSION */
117 "594200", /* IDENTIFICATION_NUMBER */
118 "", /* MAJOR_SW_VERSION */
119 "", /* MINOR_SW_VERSION */
120};
121
122static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
123 "CMU", /* DEVICE_NAME */
124 "1", /* GENERATION */
125 "CMU1", /* PCB_NAME */
126 "Q", /* FORM */
127 "A", /* VERSION */
128 "594128", /* IDENTIFICATION_NUMBER */
129 "", /* MAJOR_SW_VERSION */
130 "", /* MINOR_SW_VERSION */
131};
132
133
134/* list of known modules */
135static char **hw_id_list[] = {
136 cm1_qa_hw_id,
137 cm11_qa_hw_id,
138 cmu1_qa_hw_id,
139};
140
Wolfgang Denkbe5d72d2007-08-13 21:57:53 +0200141/* indices to the above list - keep in sync */
Bartlomiej Sieka86b116b2007-08-03 12:08:16 +0200142enum {
143 CM1_QA,
144 CM11_QA,
145 CMU1_QA,
146};
147
148
149/* identify modules based on these hw id elements */
150static int hw_id_identify[] = {
151 PCB_NAME,
152 FORM,
153 VERSION,
154};
155
156
157/* Registers' settings for SDRAM controller intialization */
158typedef struct {
159 ulong mode;
160 ulong control;
161 ulong config1;
162 ulong config2;
163} mem_conf_t;
164
165static mem_conf_t k4s561632E = {
166 0x00CD0000, /* CASL 3, burst length 8 */
167 0x514F0000,
168 0xE2333900,
169 0x8EE70000
170};
171
172static mem_conf_t mt48lc32m16a2 = {
173 0x00CD0000, /* CASL 3, burst length 8 */
174 0x514F0000,
175 0xD2322800,
176 0x8AD70000
177};
178
179static mem_conf_t* memory_config[] = {
180 &k4s561632E,
181 &mt48lc32m16a2
182};
183
184#endif /* _CM5200_H */