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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a6e34f76c51c8514f1b691fc60394f09ae4fb2ff / . / board / st / nhk8815 / platform.S
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Alessandro Rubinid5254f12009-01-24 18:10:37 +0100[diff] [blame]1/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2005
5 * STMicrolelctronics, <www.st.com>
6 *
7 * (C) Copyright 2004, ARM Ltd.
8 * Philippe Robin, <philippe.robin@arm.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <config.h>
30#include <version.h>
31
32.globl lowlevel_init
33lowlevel_init:
34 /* Jump to the flash address */
35 ldr r0, =CFG_ONENAND_BASE
36
37 /*
38 * Make it independent whether we boot from 0x0 or 0x30000000.
39 * Non-portable: it relies on the knowledge that ip has to be updated
40 */
41 orr ip, ip, r0 /* adjust return address of cpu_init_crit */
42 orr lr, lr, r0 /* adjust return address */
43 orr pc, pc, r0 /* jump to the normal address */
44 nop
45
46 /* Initialize PLL, Remap clear, FSMC, MPMC here! */
47 /* What about GPIO, CLCD and UART */
48
49 /* PLL Initialization */
50 /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
51 ldr r0, =NOMADIK_SRC_BASE
52
53 ldr r1, =0x2B013502
54
55 str r1, [r0, #0x14]
56
57 /* Used to set all the timers clock to 2.4MHZ */
58 ldr r1, =0x2AAAA004
59 str r1, [r0]
60
61 ldr r1, =0x10000000
62 str r1, [r0, #0x10]
63
64 /* FSMC setup ---- */
65 ldr r0, =NOMADIK_FSMC_BASE
66
67 ldr r1, =0x10DB /* For 16-bit NOR flash */
68 str r1, [r0, #0x08]
69
70 ldr r1, =0x03333333 /* For 16-bit NOR flash */
71 str r1, [r0, #0xc]
72
73 /* oneNAND setting */
74 ldr r1, =0x0000105B /* BCR0 Prog control register */
75 str r1, [r0]
76
77 ldr r1, =0x0A200551 /* BTR0 Prog timing register */
78 str r1, [r0, #0x04]
79
80 /* preload the instructions into icache */
81 add r0, pc, #0x1F
82 bic r0, r0, #0x1F
83 mcr p15, 0, r0, c7, c13, 1
84 add r0, r0, #0x20
85 mcr p15, 0, r0, c7, c13, 1
86
87 /* Now Clear Remap */
88 ldr r0, =NOMADIK_SRC_BASE
89
90 ldr r1, =0x2004
91 str r1, [r0]
92
93 ldr r1, =0x10000000
94 str r1, [r0, #0x10]
95
96 ldr r0, =0x101E9000
97 ldr r1, =0x2004
98 str r1, [r0]
99
100 ldr r0, =NOMADIK_SRC_BASE
101 ldr r1, =0x2104
102 str r1, [r0]
103
104 /* FSMC setup -- */
105 mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
106 orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
107
108 ldr r1, =0x10DB /* For 16-bit NOR flash */
109 str r1, [r0, #0x8]
110
111 ldr r1, =0x03333333 /* For 16-bit NOR flash */
112 str r1, [r0, #0xc]
113
114 /* MPMC Setup */
115 ldr r0, =NOMADIK_MPMC_BASE
116
117 ldr r1, =0xF00003
118 str r1, [r0] /* Enable the MPMC and the DLL */
119
120 ldr r1, =0x183
121 str r1, [r0, #0x20]
122
123 ldr r2, =NOMADIK_PMU_BASE
124
125 ldr r1, =0x1111
126 str r1, [r2]
127
128 ldr r1, =0x1111 /* Prog the, mand delay strategy */
129 str r1, [r0, #0x28]
130
131 ldr r1, =0x103 /* NOP ,mand */
132 str r1, [r0, #0x20]
133
134 /* FIXME -- Wait required here */
135
136 ldr r1, =0x103 /* PALL ,mand*/
137 str r1, [r0, #0x20]
138
139 ldr r1, =0x1
140 str r1, [r0, #0x24] /* To do at least two auto-refresh */
141
142 /* FIXME -- Wait required here */
143
144 /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
145 ldr r1, =0x31
146 str r1, [r0, #0x24]
147
148 /* Prog Little Endian, Not defined in 8800 board */
149 ldr r1, =0x0
150 str r1, [r0, #0x8]
151
152
153 ldr r1, =0x2
154 str r1, [r0, #0x30] /* Prog tRP timing */
155
156 ldr r1, =0x4 /* Change for 8815 */
157 str r1, [r0, #0x34] /* Prog tRAS timing */
158
159 ldr r1, =0xB
160 str r1, [r0, #0x38] /* Prog tSREX timing */
161
162
163 ldr r1, =0x1
164 str r1, [r0, #0x44] /* Prog tWR timing */
165
166 ldr r1, =0x8
167 str r1, [r0, #0x48] /* Prog tRC timing */
168
169 ldr r1, =0xA
170 str r1, [r0, #0x4C] /* Prog tRFC timing */
171
172 ldr r1, =0xB
173 str r1, [r0, #0x50] /* Prog tXSR timing */
174
175 ldr r1, =0x1
176 str r1, [r0, #0x54] /* Prog tRRD timing */
177
178 ldr r1, =0x1
179 str r1, [r0, #0x58] /* Prog tMRD timing */
180
181 ldr r1, =0x1
182 str r1, [r0, #0x5C] /* Prog tCDLR timing */
183
184 /* DDR-SDRAM MEMORY IS ON BANK0 8815 */
185 ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */
186 str r1, [r0, #0x104]
187
188 /* SDR-SDRAM MEMORY IS ON BANK1 8815 */
189 ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */
190 str r1, [r0, #0x124]
191 /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
192 /* DDR-SDRAM MEMORY IS ON BANK0*/
193
194 ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */
195 str r1, [r0, #0x100]
196
197 /*SDR-SDRAM MEMORY IS ON BANK1*/
198
199 ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */
200 str r1, [r0, #0x120]
201
202 ldr r1, =0x83 /*MODE Mand*/
203 str r1, [r0, #0x20]
204
205 /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
206
207 ldr r1, =0x62000 /*Data in*/
208 ldr r1, [r1]
209
210 /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
211
212 ldr r1, =0x8062000
213 ldr r1, [r1]
214
215 ldr r1, =0x003
216 str r1, [r0, #0x20]
217
218 /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
219
220 ldr r1, =0x01 /* Enable buffer 0 */
221 str r1, [r0, #0x400]
222
223 ldr r1, =0x01 /* Enable buffer 1 */
224 str r1, [r0, #0x420]
225
226 ldr r1, =0x01 /* Enable buffer 2 */
227 str r1, [r0, #0x440]
228
229 ldr r1, =0x01 /* Enable buffer 3 */
230 str r1, [r0, #0x460]
231
232 ldr r1, =0x01 /* Enable buffer 4 */
233 str r1, [r0, #0x480]
234
235 ldr r1, =0x01 /* Enable buffer 5 */
236 str r1, [r0, #0x4A0]
237
238 /* GPIO settings */
239
240 ldr r0, =NOMADIK_GPIO1_BASE
241
242 ldr r1, =0xC0600000
243 str r1, [r0, #0x20]
244
245 ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
246 str r1, [r0, #0x24]
247
248 ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
249 str r1, [r0, #0x28]
250
251 ldr r0, =NOMADIK_GPIO0_BASE
252
253 ldr r1, =0xFFFFFFFF
254 str r1, [r0, #0x20]
255
256 ldr r1, =0x00
257 str r1, [r0, #0x24]
258
259 ldr r1, =0x00
260 str r1, [r0, #0x28]
261
262 /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
263
264 ldr r0, =NOMADIK_FSMC_BASE
265
266 ldr r1, =0x10DB /* INIT FSMC bank 0 */
267 str r1, [r0, #0x00]
268
269 ldr r1, =0x0FFFFFFF
270 str r1, [r0, #0x04]
271
272 ldr r1, =0x010DB /* INIT FSMC bank 1 */
273 str r1, [r0, #0x08]
274
275 ldr r1, =0x00FFFFFFF
276 str r1, [r0, #0x0C]
277
278 ldr r0, =NOMADIK_UART0_BASE
279
280 ldr r1, =0x00000000
281 str r1, [r0, #0x30]
282
283 ldr r1, =0x0000004e
284 str r1, [r0, #0x24]
285
286 ldr r1, =0x00000008
287 str r1, [r0, #0x28]
288
289 ldr r1, =0x00000060
290 str r1, [r0, #0x2C]
291
292 ldr r1, =0x00000301
293 str r1, [r0, #0x30]
294
295 ldr r1, =0x00000066
296 str r1, [r0]
297
298 ldr r0, =NOMADIK_UART1_BASE
299
300 ldr r1, =0x00000000
301 str r1, [r0, #0x30]
302
303 ldr r1, =0x0000004e
304 str r1, [r0, #0x24]
305
306 ldr r1, =0x00000008
307 str r1, [r0, #0x28]
308
309 ldr r1, =0x00000060
310 str r1, [r0, #0x2C]
311
312 ldr r1, =0x00000301
313 str r1, [r0, #0x30]
314
315 ldr r1, =0x00000066
316 str r1, [r0]
317
318 ldr r0, =NOMADIK_UART2_BASE
319
320 ldr r1, =0x00000000
321 str r1, [r0, #0x30]
322
323 ldr r1, =0x0000004e
324 str r1, [r0, #0x24]
325
326 ldr r1, =0x00000008
327 str r1, [r0, #0x28]
328
329 ldr r1, =0x00000060
330 str r1, [r0, #0x2C]
331
332 ldr r1, =0x00000301
333 str r1, [r0, #0x30]
334
335 ldr r1, =0x00000066
336 str r1, [r0]
337
338 /* Configure CPLD to enable UART0 */
339
340 mov pc, lr