wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * U-Boot configuration for SIXNET SXNI855T CPU board. |
| 3 | * This board is based (loosely) on the Motorola FADS board, so this |
| 4 | * file is based (loosely) on config_FADS860T.h, see it for additional |
| 5 | * credits. |
| 6 | * |
| 7 | * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Memory map: |
| 31 | * |
| 32 | * ff100000 -> ff13ffff : FPGA CS1 |
| 33 | * ff030000 -> ff03ffff : EXPANSION CS7 |
| 34 | * ff020000 -> ff02ffff : DATA FLASH CS4 |
| 35 | * ff018000 -> ff01ffff : UART B CS6/UPMB |
| 36 | * ff010000 -> ff017fff : UART A CS5/UPMB |
| 37 | * ff000000 -> ff00ffff : IMAP internal to the MPC855T |
| 38 | * f8000000 -> fbffffff : FLASH CS0 up to 64MB |
| 39 | * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB |
| 40 | * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB |
| 41 | */ |
| 42 | |
| 43 | /* ------------------------------------------------------------------------- */ |
| 44 | |
| 45 | /* |
| 46 | * board/config.h - configuration options, board specific |
| 47 | */ |
| 48 | |
| 49 | #ifndef __CONFIG_H |
| 50 | #define __CONFIG_H |
| 51 | |
| 52 | /* |
| 53 | * High Level Configuration Options |
| 54 | * (easy to change) |
| 55 | */ |
| 56 | #include <mpc8xx_irq.h> |
| 57 | |
| 58 | #define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ |
| 59 | |
| 60 | /* The 855T is just a stripped 860T and needs code for 860, so for now |
| 61 | * at least define 860, 860T and 855T |
| 62 | */ |
| 63 | #define CONFIG_MPC860 1 |
| 64 | #define CONFIG_MPC860T 1 |
| 65 | #define CONFIG_MPC855T 1 |
| 66 | |
| 67 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 68 | #undef CONFIG_8xx_CONS_SMC2 |
| 69 | #undef CONFIG_8xx_CONS_SCC1 |
| 70 | #undef CONFIG_8xx_CONS_NONE |
| 71 | #define CONFIG_BAUDRATE 9600 |
| 72 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 73 | |
| 74 | #define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ |
| 75 | |
| 76 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
| 77 | |
| 78 | #if 0 |
| 79 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
| 80 | #else |
| 81 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 82 | #endif |
| 83 | |
wdenk | e2ffd59 | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 84 | #define CONFIG_HAS_ETH1 |
| 85 | |
wdenk | 506f044 | 2003-03-28 14:40:36 +0000 | [diff] [blame] | 86 | /*----------------------------------------------------------------------- |
| 87 | * Definitions for status LED |
| 88 | */ |
| 89 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 90 | |
| 91 | # define STATUS_LED_PAR im_ioport.iop_papar |
| 92 | # define STATUS_LED_DIR im_ioport.iop_padir |
| 93 | # define STATUS_LED_ODR im_ioport.iop_paodr |
| 94 | # define STATUS_LED_DAT im_ioport.iop_padat |
| 95 | |
| 96 | # define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | # define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
wdenk | 506f044 | 2003-03-28 14:40:36 +0000 | [diff] [blame] | 98 | # define STATUS_LED_STATE STATUS_LED_BLINKING |
| 99 | |
| 100 | # define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ |
| 101 | |
| 102 | # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ |
| 103 | |
| 104 | #ifdef DEV /* development (debug) settings */ |
| 105 | #define CONFIG_BOOT_LED_STATE STATUS_LED_OFF |
| 106 | #else /* production settings */ |
| 107 | #define CONFIG_BOOT_LED_STATE STATUS_LED_ON |
| 108 | #endif |
| 109 | |
| 110 | #define CONFIG_SHOW_BOOT_PROGRESS 1 |
| 111 | |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 112 | #define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ |
| 113 | #define CONFIG_BOOTARGS "root=/dev/ram ip=off" |
| 114 | |
| 115 | #define CONFIG_MISC_INIT_R /* have misc_init_r() function */ |
| 116 | #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ |
| 117 | |
| 118 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 119 | |
| 120 | #define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ |
| 121 | |
| 122 | #define CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 123 | /* |
| 124 | * Software (bit-bang) I2C driver configuration |
| 125 | */ |
| 126 | #define PB_SCL 0x00000020 /* PB 26 */ |
| 127 | #define PB_SDA 0x00000010 /* PB 27 */ |
| 128 | |
| 129 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
| 130 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
| 131 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
| 132 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
| 133 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
| 134 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
| 135 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
| 136 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
| 137 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 138 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | # define CONFIG_SYS_I2C_SPEED 50000 |
| 140 | # define CONFIG_SYS_I2C_SLAVE 0xFE |
| 141 | # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ |
| 142 | # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 143 | |
| 144 | #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 145 | #define CONFIG_MII 1 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 146 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #define CONFIG_SYS_DISCOVER_PHY |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 148 | |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 149 | |
Jon Loeliger | fe7f782 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 150 | /* |
Jon Loeliger | a1aa0bb | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 151 | * BOOTP options |
| 152 | */ |
| 153 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 154 | #define CONFIG_BOOTP_BOOTPATH |
| 155 | #define CONFIG_BOOTP_GATEWAY |
| 156 | #define CONFIG_BOOTP_HOSTNAME |
| 157 | |
| 158 | |
| 159 | /* |
Jon Loeliger | fe7f782 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 160 | * Command line configuration. |
| 161 | */ |
| 162 | #include <config_cmd_default.h> |
| 163 | |
| 164 | #define CONFIG_CMD_EEPROM |
| 165 | #define CONFIG_CMD_JFFS2 |
Jon Loeliger | fe7f782 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 166 | #define CONFIG_CMD_DATE |
| 167 | |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 168 | /* |
| 169 | * Miscellaneous configurable options |
| 170 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_LONGHELP /* undef to save a little memory */ |
| 172 | #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ |
Jon Loeliger | fe7f782 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 173 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 175 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 177 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 179 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 180 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 181 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
| 183 | #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 184 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 185 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 188 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 190 | |
| 191 | /* |
| 192 | * Low Level Configuration Settings |
| 193 | * (address mappings, register initial values, etc.) |
| 194 | * You should know what you are doing if you make changes here. |
| 195 | */ |
| 196 | /*----------------------------------------------------------------------- |
| 197 | * Internal Memory Mapped Register |
| 198 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_IMMR 0xFF000000 |
| 200 | #define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 201 | |
| 202 | /*----------------------------------------------------------------------- |
| 203 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 204 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 205 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 206 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
| 207 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
| 208 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 209 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 210 | |
| 211 | /*----------------------------------------------------------------------- |
| 212 | * Start addresses for the final memory configuration |
| 213 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 215 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 217 | #define CONFIG_SYS_SRAM_BASE 0xF4000000 |
| 218 | #define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 219 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 220 | #define CONFIG_SYS_FLASH_BASE 0xF8000000 |
| 221 | #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 222 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ |
| 224 | #define CONFIG_SYS_DFLASH_SIZE 0x00010000 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 225 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ |
| 227 | #define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */ |
| 228 | #define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 229 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 230 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 231 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 232 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 233 | |
| 234 | /* |
| 235 | * For booting Linux, the board info and command line data |
| 236 | * have to be in the first 8 MB of memory, since this is |
| 237 | * the maximum mapped by the Linux kernel during initialization. |
| 238 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 240 | /*----------------------------------------------------------------------- |
| 241 | * FLASH organization |
| 242 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 244 | /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. |
| 245 | * AMD 29LV641 has 128 64K sectors in 8MB |
| 246 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 248 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 250 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 251 | |
| 252 | /*----------------------------------------------------------------------- |
| 253 | * Cache Configuration |
| 254 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 255 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | fe7f782 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 256 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 258 | #endif |
| 259 | |
| 260 | /*----------------------------------------------------------------------- |
| 261 | * SYPCR - System Protection Control 11-9 |
| 262 | * SYPCR can only be written once after reset! |
| 263 | *----------------------------------------------------------------------- |
| 264 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 265 | */ |
| 266 | #if defined(CONFIG_WATCHDOG) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 268 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 269 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 271 | #endif |
| 272 | |
| 273 | /*----------------------------------------------------------------------- |
| 274 | * SIUMCR - SIU Module Configuration 11-6 |
| 275 | *----------------------------------------------------------------------- |
| 276 | * PCMCIA config., multi-function pin tri-state |
| 277 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 279 | |
| 280 | /*----------------------------------------------------------------------- |
| 281 | * TBSCR - Time Base Status and Control 11-26 |
| 282 | *----------------------------------------------------------------------- |
| 283 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 284 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 286 | |
| 287 | /*----------------------------------------------------------------------- |
| 288 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 289 | *----------------------------------------------------------------------- |
| 290 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 291 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 292 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 293 | |
| 294 | /*----------------------------------------------------------------------- |
| 295 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 296 | *----------------------------------------------------------------------- |
| 297 | * set the PLL, the low-power modes and the reset control (15-29) |
| 298 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 300 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
| 301 | |
| 302 | /*----------------------------------------------------------------------- |
| 303 | * SCCR - System Clock and reset Control Register 15-27 |
| 304 | *----------------------------------------------------------------------- |
| 305 | * Set clock output, timebase and RTC source and divider, |
| 306 | * power management and some other internal clocks |
| 307 | */ |
| 308 | #define SCCR_MASK SCCR_EBDF11 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | #define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 310 | |
| 311 | /*----------------------------------------------------------------------- |
| 312 | * |
| 313 | *----------------------------------------------------------------------- |
| 314 | * |
| 315 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | #define CONFIG_SYS_DER 0 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 317 | |
| 318 | /* Because of the way the 860 starts up and assigns CS0 the |
| 319 | * entire address space, we have to set the memory controller |
| 320 | * differently. Normally, you write the option register |
| 321 | * first, and then enable the chip select by writing the |
| 322 | * base register. For CS0, you must write the base register |
| 323 | * first, followed by the option register. |
| 324 | */ |
| 325 | |
| 326 | /* |
| 327 | * Init Memory Controller: |
| 328 | * |
| 329 | ********************************************************** |
| 330 | * BR0 and OR0 (FLASH) |
| 331 | */ |
| 332 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 333 | #define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 334 | |
| 335 | /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 336 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 337 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 338 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 339 | |
| 340 | #define CONFIG_FLASH_16BIT |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 341 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) |
| 342 | #define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 343 | |
| 344 | /********************************************************** |
| 345 | * BR1 and OR1 (FPGA) |
| 346 | * These preliminary values are also the final values. |
| 347 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 348 | #define CONFIG_SYS_OR_TIMING_FPGA \ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 349 | (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 350 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
| 351 | #define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 352 | |
| 353 | /********************************************************** |
| 354 | * BR4 and OR4 (data flash) |
| 355 | * These preliminary values are also the final values. |
| 356 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 357 | #define CONFIG_SYS_OR_TIMING_DFLASH \ |
wdenk | 7a8e9bed | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 358 | (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 359 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
| 360 | #define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 361 | |
| 362 | /********************************************************** |
| 363 | * BR5/6 and OR5/6 (Dual UART) |
| 364 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 365 | #define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ |
| 366 | #define CONFIG_SYS_DUARTA_BASE 0xff010000 |
| 367 | #define CONFIG_SYS_DUARTB_BASE 0xff018000 |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 368 | |
| 369 | #define DUART_MBMR 0 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 370 | #define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 371 | #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) |
| 373 | #define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 374 | |
| 375 | /********************************************************** |
| 376 | * |
| 377 | * Boot Flags |
| 378 | */ |
| 379 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 380 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 381 | |
| 382 | #define CONFIG_RESET_ON_PANIC /* reset if system panic() */ |
| 383 | |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 384 | #define CONFIG_ENV_IS_IN_FLASH |
| 385 | #ifdef CONFIG_ENV_IS_IN_FLASH |
wdenk | 7205e40 | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 386 | /* environment is in FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 387 | #define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ |
| 388 | #define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ |
| 389 | #define CONFIG_ENV_SECT_SIZE 0x00010000 |
| 390 | #define CONFIG_ENV_SIZE 0x00002000 |
wdenk | 7205e40 | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 391 | #else |
| 392 | /* environment is in EEPROM */ |
Jean-Christophe PLAGNIOL-VILLARD | bb1f8b4 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 393 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 394 | #define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */ |
| 395 | #define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/ |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 396 | #endif |
| 397 | |
| 398 | #if 1 |
| 399 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
Wolfgang Denk | c37207d | 2008-07-16 16:38:59 +0200 | [diff] [blame] | 400 | #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay |
wdenk | cc1c8a1 | 2002-11-02 22:58:18 +0000 | [diff] [blame] | 401 | #define CONFIG_AUTOBOOT_DELAY_STR "delayabit" |
| 402 | #define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ |
| 403 | #endif |
| 404 | |
| 405 | #endif /* __CONFIG_H */ |